From mboxrd@z Thu Jan 1 00:00:00 1970 From: Fabiano Rosas Date: Mon, 08 Mar 2021 15:26:49 +0000 Subject: Re: [PATCH v3 01/41] KVM: PPC: Book3S HV: Disallow LPCR[AIL] to be set to 1 or 2 Message-Id: <87blbtmzt2.fsf@linux.ibm.com> List-Id: References: <20210305150638.2675513-1-npiggin@gmail.com> <20210305150638.2675513-2-npiggin@gmail.com> In-Reply-To: <20210305150638.2675513-2-npiggin@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: Nicholas Piggin , kvm-ppc@vger.kernel.org Cc: linuxppc-dev@lists.ozlabs.org, Nicholas Piggin Nicholas Piggin writes: > These are already disallowed by H_SET_MODE from the guest, also disallow > these by updating LPCR directly. > > AIL modes can affect the host interrupt behaviour while the guest LPCR > value is set, so filter it here too. > > Suggested-by: Fabiano Rosas > Signed-off-by: Nicholas Piggin > --- > arch/powerpc/kvm/book3s_hv.c | 11 +++++++++-- > arch/powerpc/kvm/book3s_hv_nested.c | 7 +++++-- > 2 files changed, 14 insertions(+), 4 deletions(-) > > diff --git a/arch/powerpc/kvm/book3s_hv.c b/arch/powerpc/kvm/book3s_hv.c > index 13bad6bf4c95..c40eeb20be39 100644 > --- a/arch/powerpc/kvm/book3s_hv.c > +++ b/arch/powerpc/kvm/book3s_hv.c > @@ -803,7 +803,10 @@ static int kvmppc_h_set_mode(struct kvm_vcpu *vcpu, unsigned long mflags, > vcpu->arch.dawrx1 = value2; > return H_SUCCESS; > case H_SET_MODE_RESOURCE_ADDR_TRANS_MODE: > - /* KVM does not support mflags=2 (AIL=2) */ > + /* > + * KVM does not support mflags=2 (AIL=2) and AIL=1 is reserved. > + * Keep this in synch with kvmppc_set_lpcr. > + */ > if (mflags != 0 && mflags != 3) > return H_UNSUPPORTED_FLAG_START; > return H_TOO_HARD; > @@ -1667,8 +1670,12 @@ static void kvmppc_set_lpcr(struct kvm_vcpu *vcpu, u64 new_lpcr, > * On POWER8 and POWER9 userspace can also modify AIL (alt. interrupt loc.). > */ > mask = LPCR_DPFD | LPCR_ILE | LPCR_TC; > - if (cpu_has_feature(CPU_FTR_ARCH_207S)) > + if (cpu_has_feature(CPU_FTR_ARCH_207S)) { > mask |= LPCR_AIL; > + /* LPCR[AIL]=1/2 is disallowed */ > + if ((new_lpcr & LPCR_AIL) && (new_lpcr & LPCR_AIL) != LPCR_AIL_3) > + new_lpcr &= ~LPCR_AIL; > + } > /* > * On POWER9, allow userspace to enable large decrementer for the > * guest, whether or not the host has it enabled. > diff --git a/arch/powerpc/kvm/book3s_hv_nested.c b/arch/powerpc/kvm/book3s_hv_nested.c > index 2fe1fea4c934..b496079e02f7 100644 > --- a/arch/powerpc/kvm/book3s_hv_nested.c > +++ b/arch/powerpc/kvm/book3s_hv_nested.c > @@ -139,9 +139,12 @@ static void sanitise_hv_regs(struct kvm_vcpu *vcpu, struct hv_guest_state *hr) We're missing the patch that moves the lpcr setting into sanitise_hv_regs. > > /* > * Don't let L1 change LPCR bits for the L2 except these: > + * Keep this in sync with kvmppc_set_lpcr. > */ > - mask = LPCR_DPFD | LPCR_ILE | LPCR_TC | LPCR_AIL | LPCR_LD | > - LPCR_LPES | LPCR_MER; > + mask = LPCR_DPFD | LPCR_ILE | LPCR_TC | LPCR_LD | LPCR_LPES | LPCR_MER; I think this line's change belongs in patch 33 doesn't it? Otherwise you are clearing a bit below that is not present in the mask so it would never be used anyway. > + /* LPCR[AIL]=1/2 is disallowed */ > + if ((hr->lpcr & LPCR_AIL) && (hr->lpcr & LPCR_AIL) != LPCR_AIL_3) > + hr->lpcr &= ~LPCR_AIL; > hr->lpcr = (vc->lpcr & ~mask) | (hr->lpcr & mask); > > /* From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B5CBBC433DB for ; Mon, 8 Mar 2021 15:31:07 +0000 (UTC) Received: from lists.ozlabs.org (lists.ozlabs.org [112.213.38.117]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 258F765268 for ; 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Mon, 8 Mar 2021 15:26:52 GMT Received: from b03ledav004.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id E93307806A; Mon, 8 Mar 2021 15:26:51 +0000 (GMT) Received: from b03ledav004.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 529FB78060; Mon, 8 Mar 2021 15:26:51 +0000 (GMT) Received: from localhost (unknown [9.163.6.5]) by b03ledav004.gho.boulder.ibm.com (Postfix) with ESMTPS; Mon, 8 Mar 2021 15:26:51 +0000 (GMT) From: Fabiano Rosas To: Nicholas Piggin , kvm-ppc@vger.kernel.org Subject: Re: [PATCH v3 01/41] KVM: PPC: Book3S HV: Disallow LPCR[AIL] to be set to 1 or 2 In-Reply-To: <20210305150638.2675513-2-npiggin@gmail.com> References: <20210305150638.2675513-1-npiggin@gmail.com> <20210305150638.2675513-2-npiggin@gmail.com> Date: Mon, 08 Mar 2021 12:26:49 -0300 Message-ID: <87blbtmzt2.fsf@linux.ibm.com> MIME-Version: 1.0 Content-Type: text/plain X-TM-AS-GCONF: 00 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.369, 18.0.761 definitions=2021-03-08_11:2021-03-08, 2021-03-08 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 mlxlogscore=999 impostorscore=0 suspectscore=0 bulkscore=0 priorityscore=1501 clxscore=1015 mlxscore=0 phishscore=0 spamscore=0 malwarescore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2009150000 definitions=main-2103080083 X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linuxppc-dev@lists.ozlabs.org, Nicholas Piggin Errors-To: linuxppc-dev-bounces+linuxppc-dev=archiver.kernel.org@lists.ozlabs.org Sender: "Linuxppc-dev" Nicholas Piggin writes: > These are already disallowed by H_SET_MODE from the guest, also disallow > these by updating LPCR directly. > > AIL modes can affect the host interrupt behaviour while the guest LPCR > value is set, so filter it here too. > > Suggested-by: Fabiano Rosas > Signed-off-by: Nicholas Piggin > --- > arch/powerpc/kvm/book3s_hv.c | 11 +++++++++-- > arch/powerpc/kvm/book3s_hv_nested.c | 7 +++++-- > 2 files changed, 14 insertions(+), 4 deletions(-) > > diff --git a/arch/powerpc/kvm/book3s_hv.c b/arch/powerpc/kvm/book3s_hv.c > index 13bad6bf4c95..c40eeb20be39 100644 > --- a/arch/powerpc/kvm/book3s_hv.c > +++ b/arch/powerpc/kvm/book3s_hv.c > @@ -803,7 +803,10 @@ static int kvmppc_h_set_mode(struct kvm_vcpu *vcpu, unsigned long mflags, > vcpu->arch.dawrx1 = value2; > return H_SUCCESS; > case H_SET_MODE_RESOURCE_ADDR_TRANS_MODE: > - /* KVM does not support mflags=2 (AIL=2) */ > + /* > + * KVM does not support mflags=2 (AIL=2) and AIL=1 is reserved. > + * Keep this in synch with kvmppc_set_lpcr. > + */ > if (mflags != 0 && mflags != 3) > return H_UNSUPPORTED_FLAG_START; > return H_TOO_HARD; > @@ -1667,8 +1670,12 @@ static void kvmppc_set_lpcr(struct kvm_vcpu *vcpu, u64 new_lpcr, > * On POWER8 and POWER9 userspace can also modify AIL (alt. interrupt loc.). > */ > mask = LPCR_DPFD | LPCR_ILE | LPCR_TC; > - if (cpu_has_feature(CPU_FTR_ARCH_207S)) > + if (cpu_has_feature(CPU_FTR_ARCH_207S)) { > mask |= LPCR_AIL; > + /* LPCR[AIL]=1/2 is disallowed */ > + if ((new_lpcr & LPCR_AIL) && (new_lpcr & LPCR_AIL) != LPCR_AIL_3) > + new_lpcr &= ~LPCR_AIL; > + } > /* > * On POWER9, allow userspace to enable large decrementer for the > * guest, whether or not the host has it enabled. > diff --git a/arch/powerpc/kvm/book3s_hv_nested.c b/arch/powerpc/kvm/book3s_hv_nested.c > index 2fe1fea4c934..b496079e02f7 100644 > --- a/arch/powerpc/kvm/book3s_hv_nested.c > +++ b/arch/powerpc/kvm/book3s_hv_nested.c > @@ -139,9 +139,12 @@ static void sanitise_hv_regs(struct kvm_vcpu *vcpu, struct hv_guest_state *hr) We're missing the patch that moves the lpcr setting into sanitise_hv_regs. > > /* > * Don't let L1 change LPCR bits for the L2 except these: > + * Keep this in sync with kvmppc_set_lpcr. > */ > - mask = LPCR_DPFD | LPCR_ILE | LPCR_TC | LPCR_AIL | LPCR_LD | > - LPCR_LPES | LPCR_MER; > + mask = LPCR_DPFD | LPCR_ILE | LPCR_TC | LPCR_LD | LPCR_LPES | LPCR_MER; I think this line's change belongs in patch 33 doesn't it? Otherwise you are clearing a bit below that is not present in the mask so it would never be used anyway. > + /* LPCR[AIL]=1/2 is disallowed */ > + if ((hr->lpcr & LPCR_AIL) && (hr->lpcr & LPCR_AIL) != LPCR_AIL_3) > + hr->lpcr &= ~LPCR_AIL; > hr->lpcr = (vc->lpcr & ~mask) | (hr->lpcr & mask); > > /*