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From: "Alex Bennée" <alex.bennee@linaro.org>
To: Bin Meng <bmeng.cn@gmail.com>
Cc: Jean-Christophe Dubois <jcd@tribudubois.net>,
	Peter Maydell <peter.maydell@linaro.org>,
	qemu-devel@nongnu.org, Bin Meng <bin.meng@windriver.com>,
	qemu-arm@nongnu.org
Subject: Re: [PATCH 1/3] hw/misc: imx6_ccm: Update PMU_MISC0 reset value
Date: Mon, 14 Dec 2020 10:26:50 +0000	[thread overview]
Message-ID: <87blewvftl.fsf@linaro.org> (raw)
In-Reply-To: <1607937538-69471-2-git-send-email-bmeng.cn@gmail.com>


Bin Meng <bmeng.cn@gmail.com> writes:

> From: Bin Meng <bin.meng@windriver.com>
>
> U-Boot expects PMU_MISC0 register bit 7 is set (see init_bandgap()
> in arch/arm/mach-imx/mx6/soc.c) during boot. This bit indicates the
> bandgap has stabilized.
>
> With this change, the latest upstream U-Boot (v2021.01-rc3) for imx6
> sabrelite board (mx6qsabrelite_defconfig), with a slight change made
> by switching CONFIG_OF_SEPARATE to CONFIG_OF_EMBED, boots to U-Boot
> shell on QEMU with the following command:
>
> $ qemu-system-arm -M sabrelite -m 1G -kernel u-boot -display none \
>     -serial null -serial stdio
>
> Boot log below:
>
>   U-Boot 2021.01-rc3 (Dec 12 2020 - 17:40:02 +0800)
>
>   CPU:   Freescale i.MX?? rev1.0 at 792 MHz
>   Reset cause: POR
>   Model: Freescale i.MX6 Quad SABRE Lite Board
>   Board: SABRE Lite
>   I2C:   ready
>   DRAM:  1 GiB
>   force_idle_bus: sda=0 scl=0 sda.gp=0x5c scl.gp=0x55
>   force_idle_bus: failed to clear bus, sda=0 scl=0
>   force_idle_bus: sda=0 scl=0 sda.gp=0x6d scl.gp=0x6c
>   force_idle_bus: failed to clear bus, sda=0 scl=0
>   force_idle_bus: sda=0 scl=0 sda.gp=0xcb scl.gp=0x5
>   force_idle_bus: failed to clear bus, sda=0 scl=0
>   MMC:   FSL_SDHC: 0, FSL_SDHC: 1
>   Loading Environment from MMC... *** Warning - No block device, using default environment
>
>   In:    serial
>   Out:   serial
>   Err:   serial
>   Net:   Board Net Initialization Failed
>   No ethernet found.
>   starting USB...
>   Bus usb@2184000: usb dr_mode not found
>   USB EHCI 1.00
>   Bus usb@2184200: USB EHCI 1.00
>   scanning bus usb@2184000 for devices... 1 USB Device(s) found
>   scanning bus usb@2184200 for devices... 1 USB Device(s) found
>          scanning usb for storage devices... 0 Storage Device(s) found
>          scanning usb for ethernet devices... 0 Ethernet Device(s) found
>   Hit any key to stop autoboot:  0
>   =>
>
> Signed-off-by: Bin Meng <bin.meng@windriver.com>
> ---
>
>  hw/misc/imx6_ccm.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/hw/misc/imx6_ccm.c b/hw/misc/imx6_ccm.c
> index cb74042..7e031b6 100644
> --- a/hw/misc/imx6_ccm.c
> +++ b/hw/misc/imx6_ccm.c
> @@ -450,7 +450,7 @@ static void imx6_ccm_reset(DeviceState *dev)
>      s->analog[PMU_REG_3P0] = 0x00000F74;
>      s->analog[PMU_REG_2P5] = 0x00005071;
>      s->analog[PMU_REG_CORE] = 0x00402010;
> -    s->analog[PMU_MISC0] = 0x04000000;
> +    s->analog[PMU_MISC0] = 0x04000080;

Are the registers different on the imx6ul machine or should a similar
change be made to imx6ul_ccm_reset?

Also what is the write behaviour of this bit? If it is RAO/WI then
analog_mask needs fixing so a write to the register doesn't reset the
state.

>      s->analog[PMU_MISC1] = 0x00000000;
>      s->analog[PMU_MISC2] = 0x00272727;


-- 
Alex Bennée

WARNING: multiple messages have this Message-ID (diff)
From: "Alex Bennée" <alex.bennee@linaro.org>
To: Bin Meng <bmeng.cn@gmail.com>
Cc: Peter Maydell <peter.maydell@linaro.org>,
	Bin Meng <bin.meng@windriver.com>,
	qemu-devel@nongnu.org, qemu-arm@nongnu.org,
	Jean-Christophe Dubois <jcd@tribudubois.net>
Subject: Re: [PATCH 1/3] hw/misc: imx6_ccm: Update PMU_MISC0 reset value
Date: Mon, 14 Dec 2020 10:26:50 +0000	[thread overview]
Message-ID: <87blewvftl.fsf@linaro.org> (raw)
In-Reply-To: <1607937538-69471-2-git-send-email-bmeng.cn@gmail.com>


Bin Meng <bmeng.cn@gmail.com> writes:

> From: Bin Meng <bin.meng@windriver.com>
>
> U-Boot expects PMU_MISC0 register bit 7 is set (see init_bandgap()
> in arch/arm/mach-imx/mx6/soc.c) during boot. This bit indicates the
> bandgap has stabilized.
>
> With this change, the latest upstream U-Boot (v2021.01-rc3) for imx6
> sabrelite board (mx6qsabrelite_defconfig), with a slight change made
> by switching CONFIG_OF_SEPARATE to CONFIG_OF_EMBED, boots to U-Boot
> shell on QEMU with the following command:
>
> $ qemu-system-arm -M sabrelite -m 1G -kernel u-boot -display none \
>     -serial null -serial stdio
>
> Boot log below:
>
>   U-Boot 2021.01-rc3 (Dec 12 2020 - 17:40:02 +0800)
>
>   CPU:   Freescale i.MX?? rev1.0 at 792 MHz
>   Reset cause: POR
>   Model: Freescale i.MX6 Quad SABRE Lite Board
>   Board: SABRE Lite
>   I2C:   ready
>   DRAM:  1 GiB
>   force_idle_bus: sda=0 scl=0 sda.gp=0x5c scl.gp=0x55
>   force_idle_bus: failed to clear bus, sda=0 scl=0
>   force_idle_bus: sda=0 scl=0 sda.gp=0x6d scl.gp=0x6c
>   force_idle_bus: failed to clear bus, sda=0 scl=0
>   force_idle_bus: sda=0 scl=0 sda.gp=0xcb scl.gp=0x5
>   force_idle_bus: failed to clear bus, sda=0 scl=0
>   MMC:   FSL_SDHC: 0, FSL_SDHC: 1
>   Loading Environment from MMC... *** Warning - No block device, using default environment
>
>   In:    serial
>   Out:   serial
>   Err:   serial
>   Net:   Board Net Initialization Failed
>   No ethernet found.
>   starting USB...
>   Bus usb@2184000: usb dr_mode not found
>   USB EHCI 1.00
>   Bus usb@2184200: USB EHCI 1.00
>   scanning bus usb@2184000 for devices... 1 USB Device(s) found
>   scanning bus usb@2184200 for devices... 1 USB Device(s) found
>          scanning usb for storage devices... 0 Storage Device(s) found
>          scanning usb for ethernet devices... 0 Ethernet Device(s) found
>   Hit any key to stop autoboot:  0
>   =>
>
> Signed-off-by: Bin Meng <bin.meng@windriver.com>
> ---
>
>  hw/misc/imx6_ccm.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/hw/misc/imx6_ccm.c b/hw/misc/imx6_ccm.c
> index cb74042..7e031b6 100644
> --- a/hw/misc/imx6_ccm.c
> +++ b/hw/misc/imx6_ccm.c
> @@ -450,7 +450,7 @@ static void imx6_ccm_reset(DeviceState *dev)
>      s->analog[PMU_REG_3P0] = 0x00000F74;
>      s->analog[PMU_REG_2P5] = 0x00005071;
>      s->analog[PMU_REG_CORE] = 0x00402010;
> -    s->analog[PMU_MISC0] = 0x04000000;
> +    s->analog[PMU_MISC0] = 0x04000080;

Are the registers different on the imx6ul machine or should a similar
change be made to imx6ul_ccm_reset?

Also what is the write behaviour of this bit? If it is RAO/WI then
analog_mask needs fixing so a write to the register doesn't reset the
state.

>      s->analog[PMU_MISC1] = 0x00000000;
>      s->analog[PMU_MISC2] = 0x00272727;


-- 
Alex Bennée


  reply	other threads:[~2020-12-14 10:32 UTC|newest]

Thread overview: 18+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-12-14  9:18 [PATCH 0/3] hw/arm: sabrelite: Improve emulation fidelity to allow booting upstream U-Boot Bin Meng
2020-12-14  9:18 ` [PATCH 1/3] hw/misc: imx6_ccm: Update PMU_MISC0 reset value Bin Meng
2020-12-14 10:26   ` Alex Bennée [this message]
2020-12-14 10:26     ` Alex Bennée
2020-12-14 10:43     ` Bin Meng
2020-12-14 10:43       ` Bin Meng
2020-12-14 15:02       ` Alex Bennée
2020-12-14 19:05       ` Alex Bennée
2020-12-14  9:18 ` [PATCH 2/3] hw/msic: imx6_ccm: Correct register value for silicon type Bin Meng
2020-12-14  9:18 ` [PATCH 3/3] hw/arm: sabrelite: Connect the Ethernet PHY at address 6 Bin Meng
2020-12-14 10:40   ` Alex Bennée
2020-12-14 10:40     ` Alex Bennée
2020-12-14 10:50     ` Bin Meng
2020-12-14 10:50       ` Bin Meng
2020-12-14 10:23 ` [PATCH 0/3] hw/arm: sabrelite: Improve emulation fidelity to allow booting upstream U-Boot Alex Bennée
2020-12-14 10:23   ` Alex Bennée
2020-12-14 10:30   ` Bin Meng
2020-12-14 10:30     ` Bin Meng

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