From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 57B6BC43331 for ; Mon, 30 Mar 2020 15:55:35 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 26373206CC for ; Mon, 30 Mar 2020 15:55:35 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 26373206CC Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id A4F266E437; Mon, 30 Mar 2020 15:55:34 +0000 (UTC) Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by gabe.freedesktop.org (Postfix) with ESMTPS id A39966E437 for ; Mon, 30 Mar 2020 15:55:33 +0000 (UTC) IronPort-SDR: Du20guUdw+bO5+9pU2/79l04k/sDRUCbHYPjwEXmB70POYoTlzb8QY4sEr7w5TSvOd+hGbNc+q WXWJd6GGZrRg== X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Mar 2020 08:55:33 -0700 IronPort-SDR: rE5B1idAWVwp41qvvtosyf+OKGqcvbaPVck15RxYeAkW5H7l8wn2N8HYOjkNEd63hfh7bxnaVf 2NpQ1HGCmZiw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.72,324,1580803200"; d="scan'208";a="242065943" Received: from adixit-mobl.amr.corp.intel.com (HELO adixit-arch.intel.com) ([10.212.185.90]) by orsmga008.jf.intel.com with ESMTP; 30 Mar 2020 08:55:32 -0700 Date: Mon, 30 Mar 2020 08:55:32 -0700 Message-ID: <87blodrg5n.wl-ashutosh.dixit@intel.com> From: "Dixit, Ashutosh" To: Chris Wilson In-Reply-To: <158556296041.3228.10327206845355852563@build.alporthouse.com> References: <20200330091411.37357-1-lionel.g.landwerlin@intel.com> <158556296041.3228.10327206845355852563@build.alporthouse.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM/1.14.9 (=?ISO-8859-4?Q?Goj=F2?=) APEL/10.8 EasyPG/1.0.0 Emacs/26 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Subject: Re: [Intel-gfx] [PATCH] drm/i915/perf: don't read head/tail pointers outside critical section X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: intel-gfx@lists.freedesktop.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" On Mon, 30 Mar 2020 03:09:20 -0700, Chris Wilson wrote: > > Quoting Lionel Landwerlin (2020-03-30 10:14:11) > > Reading or writing those fields should only happen under > > stream->oa_buffer.ptr_lock. > > Writing, yes. Reading as a pair, sure. There are other ways you can > ensure that the tail/head are read as one, but fair enough. Sorry but I am trying to understand exactly what the purpose of stream->oa_buffer.ptr_lock is? This is a classic ring buffer producer consumer situation where producer updates tail and consumer updates head. Since both are u32's can't those operations be done without requiring a lock? > > > Signed-off-by: Lionel Landwerlin > > Fixes: d1df41eb72ef ("drm/i915/perf: rework aging tail workaround") > > --- > > drivers/gpu/drm/i915/i915_perf.c | 8 ++++++-- > > 1 file changed, 6 insertions(+), 2 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c > > index c74ebac50015..ec9421f02ebd 100644 > > --- a/drivers/gpu/drm/i915/i915_perf.c > > +++ b/drivers/gpu/drm/i915/i915_perf.c > > @@ -463,6 +463,7 @@ static bool oa_buffer_check_unlocked(struct i915_perf_stream *stream) > > u32 gtt_offset = i915_ggtt_offset(stream->oa_buffer.vma); > > int report_size = stream->oa_buffer.format_size; > > unsigned long flags; > > + bool pollin; > > u32 hw_tail; > > u64 now; > > > > @@ -532,10 +533,13 @@ static bool oa_buffer_check_unlocked(struct i915_perf_stream *stream) > > stream->oa_buffer.aging_timestamp = now; > > } > > > > + pollin = OA_TAKEN(stream->oa_buffer.tail - gtt_offset, > > + stream->oa_buffer.head - gtt_offset) >= report_size; > > + > > + > > Bonus \n > > Reviewed-by: Chris Wilson > > > spin_unlock_irqrestore(&stream->oa_buffer.ptr_lock, flags); > > > > - return OA_TAKEN(stream->oa_buffer.tail - gtt_offset, > > - stream->oa_buffer.head - gtt_offset) >= report_size; > > + return pollin; In what way is the original code incorrect? As I mentioned head is u32 and can be read atomically without requiring a lock? We had deliberately moved this code outside the lock so as to pick up the the latest value of head if it had been updated in the consumer (read). _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx