From: "Alex Bennée" <alex.bennee@linaro.org>
To: qemu-devel@nongnu.org
Cc: peter.maydell@linaro.org, qemu-stable@nongnu.org,
Jeff Kubascik <jeff.kubascik@dornerworks.com>
Subject: Re: [PATCH] target/arm: Set ISSIs16Bit in make_issinfo
Date: Fri, 20 Dec 2019 13:35:27 +0000 [thread overview]
Message-ID: <87bls3dsrk.fsf@linaro.org> (raw)
In-Reply-To: <20191219185609.16748-1-richard.henderson@linaro.org>
Richard Henderson <richard.henderson@linaro.org> writes:
> During the conversion to decodetree, the setting of
> ISSIs16Bit got lost. This causes the guest os to
> incorrectly adjust trapping memory operations.
>
> Fixes: 46beb58efbb8a2a32
It's not really obvious from this commit where we end up now calling...
> Cc: qemu-stable@nongnu.org
> Reported-by: Jeff Kubascik <jeff.kubascik@dornerworks.com>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> target/arm/translate.c | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/target/arm/translate.c b/target/arm/translate.c
> index 2b6c1f91bf..9f0afbdb75 100644
> --- a/target/arm/translate.c
> +++ b/target/arm/translate.c
> @@ -8556,6 +8556,9 @@ static ISSInfo make_issinfo(DisasContext *s, int rd, bool p, bool w)
> /* ISS not valid if writeback */
> if (p && !w) {
> ret = rd;
> + if (s->base.pc_next - s->pc_curr == 2) {
> + ret |= ISSIs16Bit;
> + }
this function.
Should I be seeing op_load_rr/ri in the included generated functions?
> } else {
> ret = ISSInvalid;
> }
--
Alex Bennée
next prev parent reply other threads:[~2019-12-20 13:36 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-12-19 18:56 [PATCH] target/arm: Set ISSIs16Bit in make_issinfo Richard Henderson
2019-12-20 13:35 ` Alex Bennée [this message]
2019-12-20 13:48 ` Peter Maydell
2020-01-03 12:56 ` Peter Maydell
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