From mboxrd@z Thu Jan 1 00:00:00 1970 From: Jiong Wang Subject: Re: [PATCH bpf-next 2/7] ppc: bpf: implement jitting of BPF_ALU | BPF_ARSH | BPF_* Date: Wed, 05 Dec 2018 11:28:32 +0000 Message-ID: <87bm60gqlb.fsf@netronome.com> References: <1543956922-8620-1-git-send-email-jiong.wang@netronome.com> <1543956922-8620-3-git-send-email-jiong.wang@netronome.com> <7664a4d2-ed4e-4e60-2d1d-3b113d05972b@linux.ibm.com> Mime-Version: 1.0 Content-Type: text/plain Cc: Jiong Wang , daniel@iogearbox.net, ast@kernel.org, netdev@vger.kernel.org, oss-drivers@netronome.com, "Naveen N . Rao" To: Sandipan Das Return-path: Received: from mail-wr1-f67.google.com ([209.85.221.67]:42183 "EHLO mail-wr1-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726937AbeLEL2h (ORCPT ); Wed, 5 Dec 2018 06:28:37 -0500 Received: by mail-wr1-f67.google.com with SMTP id q18so19271335wrx.9 for ; Wed, 05 Dec 2018 03:28:36 -0800 (PST) In-reply-to: <7664a4d2-ed4e-4e60-2d1d-3b113d05972b@linux.ibm.com> Sender: netdev-owner@vger.kernel.org List-ID: Sandipan Das writes: > Hi Jiong, > > On 05/12/18 2:25 AM, Jiong Wang wrote: >> This patch implements code-gen for BPF_ALU | BPF_ARSH | BPF_*. >> >> Cc: Naveen N. Rao >> Cc: Sandipan Das >> Signed-off-by: Jiong Wang >> --- > [...] >> diff --git a/arch/powerpc/net/bpf_jit_comp64.c b/arch/powerpc/net/bpf_jit_comp64.c >> index 17482f5..c685b4f 100644 >> --- a/arch/powerpc/net/bpf_jit_comp64.c >> +++ b/arch/powerpc/net/bpf_jit_comp64.c >> @@ -529,9 +529,15 @@ static int bpf_jit_build_body(struct bpf_prog *fp, u32 *image, >> if (imm != 0) >> PPC_SRDI(dst_reg, dst_reg, imm); >> break; >> + case BPF_ALU | BPF_ARSH | BPF_X: /* (s32) dst >>= src */ >> + PPC_SRAW(dst_reg, dst_reg, src_reg); >> + break; > > On ppc64, the sraw and srawi instructions also use sign extension. So, you will have > to ensure that upper 32 bits are cleared. We already have a label in our JIT code > called bpf_alu32_trunc that takes care of this. Replacing the break statement with > a goto bpf_alu32_trunc will fix this. (resend the reply, got a delivery failure notification from netdev@vger.kernel.org) Indeed. Doubled checked the ISA doc,"Bit 32 of RS is replicated to fill RA0:31.". Will fix both places in v2. Thanks Regards, Jiong > >> case BPF_ALU64 | BPF_ARSH | BPF_X: /* (s64) dst >>= src */ >> PPC_SRAD(dst_reg, dst_reg, src_reg); >> break; >> + case BPF_ALU | BPF_ARSH | BPF_K: /* (s32) dst >>= imm */ >> + PPC_SRAWI(dst_reg, dst_reg, imm); >> + break; > > Same here. > >> case BPF_ALU64 | BPF_ARSH | BPF_K: /* (s64) dst >>= imm */ >> if (imm != 0) >> PPC_SRADI(dst_reg, dst_reg, imm); >> > > With Regards, > Sandipan