From mboxrd@z Thu Jan 1 00:00:00 1970 From: Mika Kuoppala Subject: Re: [PATCH] drm/i915: Perform an invalidate prior to executing golden renderstate Date: Tue, 08 Aug 2017 16:43:33 +0300 Message-ID: <87bmnq5g56.fsf@gaia.fi.intel.com> References: <20170808131904.1385-1-chris@chris-wilson.co.uk> <87k22e5ggo.fsf@gaia.fi.intel.com> <87efsm5geh.fsf@gaia.fi.intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by gabe.freedesktop.org (Postfix) with ESMTPS id 369DC6E14E for ; Tue, 8 Aug 2017 13:45:17 +0000 (UTC) In-Reply-To: <87efsm5geh.fsf@gaia.fi.intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: Chris Wilson , intel-gfx@lists.freedesktop.org Cc: stable@vger.kernel.org List-Id: intel-gfx@lists.freedesktop.org TWlrYSBLdW9wcGFsYSA8bWlrYS5rdW9wcGFsYUBsaW51eC5pbnRlbC5jb20+IHdyaXRlczoKCj4g TWlrYSBLdW9wcGFsYSA8bWlrYS5rdW9wcGFsYUBsaW51eC5pbnRlbC5jb20+IHdyaXRlczoKPgo+ PiBDaHJpcyBXaWxzb24gPGNocmlzQGNocmlzLXdpbHNvbi5jby51az4gd3JpdGVzOgo+Pgo+Pj4g QXMgd2UgbWF5IGhhdmUganVzdCBib3VuZCB0aGUgcmVuZGVyc3RhdGUgaW50byB0aGUgR0dUVCBm b3IgZXhlY3V0aW9uLCB3ZQo+Pj4gbmVlZCB0byBlbnN1cmUgdGhhdCB0aGUgR1RUIFRMQiBhcmUg YWxzbyBmbHVzaGVkLgo+Pj4KPj4+IE9uIHNuYi1ndDIsIHRoaXMgd291bGQgY2F1c2UgYSByYW5k b20gR1BVIGhhbmcgYXQgdGhlIHN0YXJ0IG9mIGEgbmV3Cj4+PiBjb250ZXh0IChlLmcuIGJvb3Qp IGFuZCBvbiBzbmItZ3QxLCBpdCB3YXMgY2F1c2luZyB0aGUgcmVuZGVyc3RhdGUgYmF0Y2gKPj4+ IHRvIHRha2UgfjEwcy4gSXQgd2FzIHRoZSBHUFUgaGFuZyB0aGF0IHJldmVhbGVkIHRoZSB0cnV0 aCwgYXMgdGhlIENTCj4+PiBnbGVlZnVsbHkgZXhlY3V0ZWQgYmV5b25kIHRoZSBlbmQgb2YgdGhl IGdvbGRlbiByZW5kZXJzdGF0ZSBiYXRjaCwgYSBnb29kCj4+PiBpbmRpY2F0b3IgZm9yIGEgR1RU IFRMQiBtaXNzLgo+Pj4KPj4+IFNpZ25lZC1vZmYtYnk6IENocmlzIFdpbHNvbiA8Y2hyaXNAY2hy aXMtd2lsc29uLmNvLnVrPgo+Pj4gQ2M6IE1pa2EgS3VvcHBhbGEgPG1pa2Eua3VvcHBhbGFAbGlu dXguaW50ZWwuY29tPgo+Pj4gQ2M6IHN0YWJsZUB2Z2VyLmtlcm5lbC5vcmcKPj4KPj4gVGhlIGZs dXNoIGhhcyBiZWVuIHRoZXJlIGJ1dCBnb3Qgc3RvbXBlZCBieToKPj4KPj4gRml4ZXM6IGRjNGJl NjA3MWEyNCAoImRybS9pOTE1OiBBZGQgZXhwbGljaXQgcmVxdWVzdCBtYW5hZ2VtZW50IHRvIGk5 MTVfZ2VtX2luaXRfaHcoKSIpCj4+Cj4+IE5vdyB3ZSBjYW4gZml4IHRoZSBnZW42IHJlbmRlcnN0 YXRlIHRvbyA7KQo+Pgo+PiBSZXZpZXdlZC1ieTogTWlrYSBLdW9wcGFsYSA8bWlrYS5rdW9wcGFs YUBpbnRlbC5jb20+Cj4KPiBPbiBoaW5kc2lnaHQsIHNob3VsZCB3ZSBhY3R1YWxseSBkbyB0aGUg Zmx1c2ggdGhyb3VnaCBhZGQgcmVxdWVzdD8KCk5vLCBhcyBpdCBpcyBub3QgdGhlcmUgYW55bW9y ZSBpbiBnZW1faW5pdF9ody4gLUVUT09NVUNIQ09GRkVFLgoKPiAtTWlrYQo+Cj4+Cj4+PiAtLS0K Pj4+ICBkcml2ZXJzL2dwdS9kcm0vaTkxNS9pOTE1X2dlbV9yZW5kZXJfc3RhdGUuYyB8IDQgKysr Kwo+Pj4gIDEgZmlsZSBjaGFuZ2VkLCA0IGluc2VydGlvbnMoKykKPj4+Cj4+PiBkaWZmIC0tZ2l0 IGEvZHJpdmVycy9ncHUvZHJtL2k5MTUvaTkxNV9nZW1fcmVuZGVyX3N0YXRlLmMgYi9kcml2ZXJz L2dwdS9kcm0vaTkxNS9pOTE1X2dlbV9yZW5kZXJfc3RhdGUuYwo+Pj4gaW5kZXggMjQxZDgyN2I4 NWZiLi4zNzAzZGM5MWVlZGEgMTAwNjQ0Cj4+PiAtLS0gYS9kcml2ZXJzL2dwdS9kcm0vaTkxNS9p OTE1X2dlbV9yZW5kZXJfc3RhdGUuYwo+Pj4gKysrIGIvZHJpdmVycy9ncHUvZHJtL2k5MTUvaTkx NV9nZW1fcmVuZGVyX3N0YXRlLmMKPj4+IEBAIC0yNDIsNiArMjQyLDEwIEBAIGludCBpOTE1X2dl bV9yZW5kZXJfc3RhdGVfZW1pdChzdHJ1Y3QgZHJtX2k5MTVfZ2VtX3JlcXVlc3QgKnJlcSkKPj4+ ICAJCQlnb3RvIGVycl91bnBpbjsKPj4+ICAJfQo+Pj4gIAo+Pj4gKwlyZXQgPSByZXEtPmVuZ2lu ZS0+ZW1pdF9mbHVzaChyZXEsIEVNSVRfSU5WQUxJREFURSk7Cj4+PiArCWlmIChyZXQpCj4+PiAr CQlnb3RvIGVycl91bnBpbjsKPj4+ICsKPj4+ICAJcmV0ID0gcmVxLT5lbmdpbmUtPmVtaXRfYmJf c3RhcnQocmVxLAo+Pj4gIAkJCQkJIHNvLT5iYXRjaF9vZmZzZXQsIHNvLT5iYXRjaF9zaXplLAo+ Pj4gIAkJCQkJIEk5MTVfRElTUEFUQ0hfU0VDVVJFKTsKPj4+IC0tIAo+Pj4gMi4xMy4zCj4gX19f X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX18KPiBJbnRlbC1nZngg bWFpbGluZyBsaXN0Cj4gSW50ZWwtZ2Z4QGxpc3RzLmZyZWVkZXNrdG9wLm9yZwo+IGh0dHBzOi8v bGlzdHMuZnJlZWRlc2t0b3Aub3JnL21haWxtYW4vbGlzdGluZm8vaW50ZWwtZ2Z4Cl9fX19fX19f X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fCkludGVsLWdmeCBtYWlsaW5n IGxpc3QKSW50ZWwtZ2Z4QGxpc3RzLmZyZWVkZXNrdG9wLm9yZwpodHRwczovL2xpc3RzLmZyZWVk ZXNrdG9wLm9yZy9tYWlsbWFuL2xpc3RpbmZvL2ludGVsLWdmeAo= From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga14.intel.com ([192.55.52.115]:35918 "EHLO mga14.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752017AbdHHNpb (ORCPT ); Tue, 8 Aug 2017 09:45:31 -0400 From: Mika Kuoppala To: Chris Wilson , intel-gfx@lists.freedesktop.org Cc: stable@vger.kernel.org Subject: Re: [PATCH] drm/i915: Perform an invalidate prior to executing golden renderstate In-Reply-To: <87efsm5geh.fsf@gaia.fi.intel.com> References: <20170808131904.1385-1-chris@chris-wilson.co.uk> <87k22e5ggo.fsf@gaia.fi.intel.com> <87efsm5geh.fsf@gaia.fi.intel.com> Date: Tue, 08 Aug 2017 16:43:33 +0300 Message-ID: <87bmnq5g56.fsf@gaia.fi.intel.com> MIME-Version: 1.0 Content-Type: text/plain Sender: stable-owner@vger.kernel.org List-ID: Mika Kuoppala writes: > Mika Kuoppala writes: > >> Chris Wilson writes: >> >>> As we may have just bound the renderstate into the GGTT for execution, we >>> need to ensure that the GTT TLB are also flushed. >>> >>> On snb-gt2, this would cause a random GPU hang at the start of a new >>> context (e.g. boot) and on snb-gt1, it was causing the renderstate batch >>> to take ~10s. It was the GPU hang that revealed the truth, as the CS >>> gleefully executed beyond the end of the golden renderstate batch, a good >>> indicator for a GTT TLB miss. >>> >>> Signed-off-by: Chris Wilson >>> Cc: Mika Kuoppala >>> Cc: stable@vger.kernel.org >> >> The flush has been there but got stomped by: >> >> Fixes: dc4be6071a24 ("drm/i915: Add explicit request management to i915_gem_init_hw()") >> >> Now we can fix the gen6 renderstate too ;) >> >> Reviewed-by: Mika Kuoppala > > On hindsight, should we actually do the flush through add request? No, as it is not there anymore in gem_init_hw. -ETOOMUCHCOFFEE. > -Mika > >> >>> --- >>> drivers/gpu/drm/i915/i915_gem_render_state.c | 4 ++++ >>> 1 file changed, 4 insertions(+) >>> >>> diff --git a/drivers/gpu/drm/i915/i915_gem_render_state.c b/drivers/gpu/drm/i915/i915_gem_render_state.c >>> index 241d827b85fb..3703dc91eeda 100644 >>> --- a/drivers/gpu/drm/i915/i915_gem_render_state.c >>> +++ b/drivers/gpu/drm/i915/i915_gem_render_state.c >>> @@ -242,6 +242,10 @@ int i915_gem_render_state_emit(struct drm_i915_gem_request *req) >>> goto err_unpin; >>> } >>> >>> + ret = req->engine->emit_flush(req, EMIT_INVALIDATE); >>> + if (ret) >>> + goto err_unpin; >>> + >>> ret = req->engine->emit_bb_start(req, >>> so->batch_offset, so->batch_size, >>> I915_DISPATCH_SECURE); >>> -- >>> 2.13.3 > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx