From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:33572) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1c4tFK-0005Wp-IV for qemu-devel@nongnu.org; Thu, 10 Nov 2016 12:34:43 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1c4tFF-0007u0-Ts for qemu-devel@nongnu.org; Thu, 10 Nov 2016 12:34:42 -0500 Received: from mail-wm0-x236.google.com ([2a00:1450:400c:c09::236]:36217) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1c4tFF-0007tT-MK for qemu-devel@nongnu.org; Thu, 10 Nov 2016 12:34:37 -0500 Received: by mail-wm0-x236.google.com with SMTP id g23so54964426wme.1 for ; Thu, 10 Nov 2016 09:34:37 -0800 (PST) References: <20161109145748.27282-1-alex.bennee@linaro.org> <20161109145748.27282-12-alex.bennee@linaro.org> <7dcc34b1-4fb2-1b6b-cd31-4739879c5a82@twiddle.net> From: Alex =?utf-8?Q?Benn=C3=A9e?= In-reply-to: <7dcc34b1-4fb2-1b6b-cd31-4739879c5a82@twiddle.net> Date: Thu, 10 Nov 2016 17:34:35 +0000 Message-ID: <87bmxn8cic.fsf@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8bit Subject: Re: [Qemu-devel] [PATCH v6 11/19] cputlb: introduce tlb_flush_* async work. List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Richard Henderson Cc: pbonzini@redhat.com, qemu-devel@nongnu.org, mttcg@greensocs.com, fred.konrad@greensocs.com, a.rigo@virtualopensystems.com, cota@braap.org, bobby.prani@gmail.com, nikunj@linux.vnet.ibm.com, mark.burton@greensocs.com, jan.kiszka@siemens.com, serge.fdrv@gmail.com, peter.maydell@linaro.org, claudio.fontana@huawei.com, Peter Crosthwaite Richard Henderson writes: > On 11/09/2016 03:57 PM, Alex Bennée wrote: >> +void tlb_flush_page_all(target_ulong addr) > > It's a nit, but when I read this I think all pages, not all cpus. > Can we rename this tlb_fluch_page_all_cpus? So to properly support ARM TLB flush semantics I want to move some of the looping in the helpers into cputlb.c so I'm thinking we'll have: tlb_flush_page_all_cpus tlb_flush_by_mmuidx_all_cpus tlb_flush_page_by_mmuidx_all_cpus Which will have the initial parameters of at least CPUState *src, bool sync Where src is the source vCPU of the flush request and sync will cause the source vCPU to schedule its work as safe work and do a cpu_loop_exit. This will allow the helpers to ensure TLB flushes are in a known state after executing the helper. In fact for ARM we'll be able to put off the reckoning until a DMB instruction comes along and we can force synchronisation at that point but I'm assuming there must be other architectures with stricter requirements. > > Otherwise, > > Reviewed-by: Richard Henderson > > > r~ -- Alex Bennée