From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:36905) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZCVWG-0004S0-8Z for qemu-devel@nongnu.org; Tue, 07 Jul 2015 12:14:53 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ZCVWC-00041K-7X for qemu-devel@nongnu.org; Tue, 07 Jul 2015 12:14:52 -0400 Received: from mail-wi0-f178.google.com ([209.85.212.178]:37405) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZCVWB-0003zL-ST for qemu-devel@nongnu.org; Tue, 07 Jul 2015 12:14:48 -0400 Received: by wiclp1 with SMTP id lp1so55855636wic.0 for ; Tue, 07 Jul 2015 09:14:47 -0700 (PDT) References: <1435330053-18733-1-git-send-email-fred.konrad@greensocs.com> <1435330053-18733-17-git-send-email-fred.konrad@greensocs.com> From: Alex =?utf-8?Q?Benn=C3=A9e?= In-reply-to: <1435330053-18733-17-git-send-email-fred.konrad@greensocs.com> Date: Tue, 07 Jul 2015 17:14:45 +0100 Message-ID: <87bnfo9c7e.fsf@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8bit Subject: Re: [Qemu-devel] [RFC PATCH V6 16/18] arm: use tlb_flush*_all List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: fred.konrad@greensocs.com Cc: mttcg@listserver.greensocs.com, peter.maydell@linaro.org, a.spyridakis@virtualopensystems.com, mark.burton@greensocs.com, agraf@suse.de, qemu-devel@nongnu.org, guillaume.delbergue@greensocs.com, pbonzini@redhat.com, alistair.francis@xilinx.com fred.konrad@greensocs.com writes: > From: KONRAD Frederic > > This just use the new mechanism to ensure that each VCPU thread flush its own > VCPU. > > Signed-off-by: KONRAD Frederic > --- > target-arm/helper.c | 45 +++++++-------------------------------------- > 1 file changed, 7 insertions(+), 38 deletions(-) > > diff --git a/target-arm/helper.c b/target-arm/helper.c > index ad3d5da..1995439 100644 > --- a/target-arm/helper.c > +++ b/target-arm/helper.c > @@ -411,41 +411,25 @@ static void tlbimvaa_write(CPUARMState *env, const ARMCPRegInfo *ri, > static void tlbiall_is_write(CPUARMState *env, const ARMCPRegInfo *ri, > uint64_t value) > { > - CPUState *other_cs; > - > - CPU_FOREACH(other_cs) { > - tlb_flush(other_cs, 1); > - } > + tlb_flush_all(1); > } > > static void tlbiasid_is_write(CPUARMState *env, const ARMCPRegInfo *ri, > uint64_t value) > { > - CPUState *other_cs; > - > - CPU_FOREACH(other_cs) { > - tlb_flush(other_cs, value == 0); > - } > + tlb_flush_all(value == 0); > } > > static void tlbimva_is_write(CPUARMState *env, const ARMCPRegInfo *ri, > uint64_t value) > { > - CPUState *other_cs; > - > - CPU_FOREACH(other_cs) { > - tlb_flush_page(other_cs, value & TARGET_PAGE_MASK); > - } > + tlb_flush_page_all(value & TARGET_PAGE_MASK); > } > > static void tlbimvaa_is_write(CPUARMState *env, const ARMCPRegInfo *ri, > uint64_t value) > { > - CPUState *other_cs; > - > - CPU_FOREACH(other_cs) { > - tlb_flush_page(other_cs, value & TARGET_PAGE_MASK); > - } > + tlb_flush_page_all(value & TARGET_PAGE_MASK); > } > > static const ARMCPRegInfo cp_reginfo[] = { > @@ -2281,34 +2265,19 @@ static void tlbi_aa64_asid_write(CPUARMState *env, const ARMCPRegInfo *ri, > static void tlbi_aa64_va_is_write(CPUARMState *env, const ARMCPRegInfo *ri, > uint64_t value) > { > - CPUState *other_cs; > - uint64_t pageaddr = sextract64(value << 12, 0, 56); > - > - CPU_FOREACH(other_cs) { > - tlb_flush_page(other_cs, pageaddr); > - } > + tlb_flush_page_all(sextract64(value << 12, 0, 56)); > } Personally I'd keep the: uint64_t pageaddr = sextract64(value << 12, 0, 56); The compiler will optimise away but the reader will now what those bits are. > > static void tlbi_aa64_vaa_is_write(CPUARMState *env, const ARMCPRegInfo *ri, > uint64_t value) > { > - CPUState *other_cs; > - uint64_t pageaddr = sextract64(value << 12, 0, 56); > - > - CPU_FOREACH(other_cs) { > - tlb_flush_page(other_cs, pageaddr); > - } > + tlb_flush_page_all(sextract64(value << 12, 0, 56)); > } ditto > > static void tlbi_aa64_asid_is_write(CPUARMState *env, const ARMCPRegInfo *ri, > uint64_t value) > { > - CPUState *other_cs; > - int asid = extract64(value, 48, 16); > - > - CPU_FOREACH(other_cs) { > - tlb_flush(other_cs, asid == 0); > - } > + tlb_flush_all(extract64(value, 48, 16) == 0); > } ditto > > static CPAccessResult aa64_zva_access(CPUARMState *env, const ARMCPRegInfo *ri) -- Alex Bennée