From: Andi Kleen <andi@firstfloor.org>
To: Harald Servat <harald.servat@bsc.es>
Cc: linux-perf-users@vger.kernel.org
Subject: Re: Sample memory references with at least a given latency?
Date: Thu, 05 Feb 2015 08:58:40 -0800 [thread overview]
Message-ID: <87bnl8jnwf.fsf@tassilo.jf.intel.com> (raw)
In-Reply-To: <54D21524.8010305@bsc.es> (Harald Servat's message of "Wed, 04 Feb 2015 13:48:36 +0100")
Harald Servat <harald.servat@bsc.es> writes:
> is there any way to configure perf to sample memory references
> through PEBS and enable the Load Latency Performance Monitoring
> Facility (section 18.7.1.2 from the Intel 64 and IA-32 Architectures
> Software Developer's Manual).
$ ocperf.py record -e mem_trans_retired.load_latency_gt_128 -a sleep 1
perf record -e
cpu/event=0xcd,umask=0x1,ldlat=0x80,name=mem_trans_retired_load_latency_gt_128/
-a sleep 1
[ perf record: Woken up 1 times to write data ]
[ perf record: Captured and wrote 0.438 MB perf.data (~19125 samples) ]
--
ak@linux.intel.com -- Speaking for myself only
next prev parent reply other threads:[~2015-02-05 16:58 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-02-04 12:48 Sample memory references with at least a given latency? Harald Servat
[not found] ` <CALbiyZw=SqhFLtzse53SW_B-JMo-+AxPGDAE9C_aBmo4X88mrA@mail.gmail.com>
2015-02-04 13:34 ` Harald Servat
2015-02-18 9:31 ` Harald Servat
[not found] ` <CALbiyZyJhUNfMNOYwJ26P-Lq+3E_xM8SpZ9CG+WR70-n_k9x8A@mail.gmail.com>
2015-02-04 14:20 ` Harald Servat
2015-02-04 14:33 ` Vince Weaver
2015-02-05 11:33 ` Manuel Selva
2015-02-05 11:39 ` Harald Servat
2015-02-05 16:58 ` Andi Kleen [this message]
2015-02-05 18:54 ` Manuel Selva
2015-02-05 18:59 ` Andi Kleen
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