From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from perceval.ideasonboard.com (perceval.ideasonboard.com [213.167.242.64]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id ED23627FD49 for ; Tue, 12 Aug 2025 13:30:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=213.167.242.64 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755005450; cv=none; b=HutEN7sslAO3/rMqhwq3qKMpHNbM5UJJ1gEGxSsLbQCPnWAoTiZHpDT305sQnDjs6eqjty1Tj79sXpJPkk9Z7zoPc/aFzv/NE0iLXtECtoe+6Xd7MhGOPdL+xwxlBGwZlzYEgRlIr16On+2WK1CXE2BmdWZR8RHFGLTEVNRbVmg= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755005450; c=relaxed/simple; bh=pxwoVk/OivdQvSju0vl3PSqNn2XM16MYOQDZs9qQ87o=; h=Message-ID:Date:MIME-Version:Subject:From:To:Cc:References: In-Reply-To:Content-Type; b=nL1kjdpfEJsv8atDR3UY19vo7STS3ANupLmAfU/2Pi3cz1l48tRAMy2AOTm5Q+NC/LJdhPpySUJg6G8QXPU6pl4LexT3ip6Qo26ztNrlANp3eMaqxlv6htpyn7bgZqA5iDlezkN/AVTZ+HNBxoZW0ChyXPdxL6FECggOg30oSec= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=ideasonboard.com; spf=pass smtp.mailfrom=ideasonboard.com; dkim=pass (1024-bit key) header.d=ideasonboard.com header.i=@ideasonboard.com header.b=FjxyJ7xO; arc=none smtp.client-ip=213.167.242.64 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=ideasonboard.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ideasonboard.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ideasonboard.com header.i=@ideasonboard.com header.b="FjxyJ7xO" Received: from [192.168.88.20] (91-158-153-178.elisa-laajakaista.fi [91.158.153.178]) by perceval.ideasonboard.com (Postfix) with ESMTPSA id 830383DC; Tue, 12 Aug 2025 15:29:53 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ideasonboard.com; s=mail; t=1755005394; bh=pxwoVk/OivdQvSju0vl3PSqNn2XM16MYOQDZs9qQ87o=; h=Date:Subject:From:To:Cc:References:In-Reply-To:From; b=FjxyJ7xOIiBWKwsmANFN4LZiW/v2Lr1GA/BrN1/qDJRq4IqVtMjYyr4waJxIEtM2U IJLKwogD8LqTVZoRIMcRYciXeslc3irsQv7J153guW57ZowTqEl2bznIviMNhDQ3Vq mTAhgW974TK9CVoKcJV/XOxM7sxe/bAHNclwidzc= Message-ID: <87cc32a7-fe1d-4d8d-b793-e3bb7e12fb7d@ideasonboard.com> Date: Tue, 12 Aug 2025 16:30:42 +0300 Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 2/4] drm/rcar-du: dsi: Remove fixed PPI lane count setup From: Tomi Valkeinen To: Marek Vasut , dri-devel@lists.freedesktop.org Cc: David Airlie , Geert Uytterhoeven , Kieran Bingham , Laurent Pinchart , Maarten Lankhorst , Magnus Damm , Maxime Ripard , Simona Vetter , Thomas Zimmermann , linux-renesas-soc@vger.kernel.org References: <20250608142636.54033-1-marek.vasut+renesas@mailbox.org> <20250608142636.54033-3-marek.vasut+renesas@mailbox.org> <64b49da6-15ae-45e1-a4af-c1f08f80cf3a@ideasonboard.com> Content-Language: en-US In-Reply-To: <64b49da6-15ae-45e1-a4af-c1f08f80cf3a@ideasonboard.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Hi, On 12/08/2025 16:18, Tomi Valkeinen wrote: > Hi, > > On 08/06/2025 17:24, Marek Vasut wrote: >> The R-Car DSI host is capable of operating in 1..4 DSI lane mode. >> Remove hard-coded 4-lane configuration from PPI register settings >> and instead configure the PPI lane count according to lane count >> information already obtained by this driver instance. >> >> Signed-off-by: Marek Vasut >> --- >> Cc: David Airlie >> Cc: Geert Uytterhoeven >> Cc: Kieran Bingham >> Cc: Laurent Pinchart >> Cc: Maarten Lankhorst >> Cc: Magnus Damm >> Cc: Maxime Ripard >> Cc: Simona Vetter >> Cc: Thomas Zimmermann >> Cc: Tomi Valkeinen >> Cc: dri-devel@lists.freedesktop.org >> Cc: linux-renesas-soc@vger.kernel.org >> --- >> drivers/gpu/drm/renesas/rcar-du/rcar_mipi_dsi.c | 2 +- >> drivers/gpu/drm/renesas/rcar-du/rcar_mipi_dsi_regs.h | 5 +---- >> 2 files changed, 2 insertions(+), 5 deletions(-) >> >> diff --git a/drivers/gpu/drm/renesas/rcar-du/rcar_mipi_dsi.c b/drivers/gpu/drm/renesas/rcar-du/rcar_mipi_dsi.c >> index 7ab8be46c7f6..373bd0040a46 100644 >> --- a/drivers/gpu/drm/renesas/rcar-du/rcar_mipi_dsi.c >> +++ b/drivers/gpu/drm/renesas/rcar-du/rcar_mipi_dsi.c >> @@ -576,7 +576,7 @@ static int rcar_mipi_dsi_startup(struct rcar_mipi_dsi *dsi, >> udelay(10); >> rcar_mipi_dsi_clr(dsi, CLOCKSET1, CLOCKSET1_UPDATEPLL); >> >> - ppisetr = PPISETR_DLEN_3 | PPISETR_CLEN; >> + ppisetr = ((BIT(dsi->lanes) - 1) & PPISETR_DLEN_MASK) | PPISETR_CLEN; >> rcar_mipi_dsi_write(dsi, PPISETR, ppisetr); >> >> rcar_mipi_dsi_set(dsi, PHYSETUP, PHYSETUP_SHUTDOWNZ); >> diff --git a/drivers/gpu/drm/renesas/rcar-du/rcar_mipi_dsi_regs.h b/drivers/gpu/drm/renesas/rcar-du/rcar_mipi_dsi_regs.h >> index b3e57217ae63..cefa7e92b5b8 100644 >> --- a/drivers/gpu/drm/renesas/rcar-du/rcar_mipi_dsi_regs.h >> +++ b/drivers/gpu/drm/renesas/rcar-du/rcar_mipi_dsi_regs.h >> @@ -80,10 +80,7 @@ >> * PHY-Protocol Interface (PPI) Registers >> */ >> #define PPISETR 0x700 >> -#define PPISETR_DLEN_0 (0x1 << 0) >> -#define PPISETR_DLEN_1 (0x3 << 0) >> -#define PPISETR_DLEN_2 (0x7 << 0) >> -#define PPISETR_DLEN_3 (0xf << 0) >> +#define PPISETR_DLEN_MASK (0xf << 0) >> #define PPISETR_CLEN BIT(8) > > Looks fine, but do you know what the TXSETR register does? It also has > LANECNT, but I don't see the driver touching that register at all. > TXSETR:LANECNT default value is 3 (4 lanes), which matches with the old > hardcoded behavior for PPISETR... So I wonder if that register should > also be set? Ah, never mind, I now saw the patch 3 =). But should it be before patch 2? Hmm, I guess that ordering is no better. Should they be combined into "support 1,2,3 datalanes" patch? Tomi