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Thu, 08 Jan 2026 09:44:34 -0800 (PST) Received: from draig.lan ([185.126.160.19]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-432bd0e175csm17451605f8f.14.2026.01.08.09.44.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 08 Jan 2026 09:44:34 -0800 (PST) Received: from draig (localhost [IPv6:::1]) by draig.lan (Postfix) with ESMTP id 3F9D35F804; Thu, 08 Jan 2026 17:44:33 +0000 (GMT) From: =?utf-8?Q?Alex_Benn=C3=A9e?= To: BALATON Zoltan Cc: qemu-devel@nongnu.org, Aurelien Jarno , Jiaxun Yang , Bastian Koppelmann , Marcel Apfelbaum , Zhao Liu , Peter Maydell , Laurent Vivier , Philippe =?utf-8?Q?Mathieu-Daud=C3=A9?= , qemu-arm@nongnu.org, Yoshinori Sato , Yanan Wang , Aleksandar Rikalo , Thomas Huth , Eduardo Habkost Subject: Re: [RFC PATCH 02/12] target/m68k: introduce env->reset_pc In-Reply-To: <7361d961-6dbf-57af-b5e6-93f32c1b2b4c@eik.bme.hu> (BALATON Zoltan's message of "Thu, 8 Jan 2026 18:14:57 +0100 (CET)") References: <20260108143423.1378674-1-alex.bennee@linaro.org> <20260108143423.1378674-3-alex.bennee@linaro.org> <7361d961-6dbf-57af-b5e6-93f32c1b2b4c@eik.bme.hu> User-Agent: mu4e 1.12.14; emacs 30.1 Date: Thu, 08 Jan 2026 17:44:33 +0000 Message-ID: <87cy3k80e6.fsf@draig.linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=alex.bennee@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org Sender: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org BALATON Zoltan writes: > On Thu, 8 Jan 2026, Alex Benn=C3=A9e wrote: >> To transition CPUs to use the multi-phase resettable logic we need to >> stash some information for the reset handlers. Arm does this with >> arm_boot_info but for m68k all we really need is the PC we should >> reset to. >> >> Signed-off-by: Alex Benn=C3=A9e >> --- >> target/m68k/cpu.h | 1 + >> 1 file changed, 1 insertion(+) >> >> diff --git a/target/m68k/cpu.h b/target/m68k/cpu.h >> index d9db6a486a8..fda015c4b7b 100644 >> --- a/target/m68k/cpu.h >> +++ b/target/m68k/cpu.h >> @@ -155,6 +155,7 @@ typedef struct CPUArchState { >> >> /* Fields from here on are preserved across CPU reset. */ >> uint64_t features; >> + uint32_t reset_pc; > > The m64k CPUs are 32 bit but should this better use some other type > like vaddr or hwaddr here? Possibly - but the underlying env->pc is also a unint32_t so I didn't see the point of adding more churn. > > Regards. > BALATON Zoltan > >> } CPUM68KState; >> >> /* >> --=20 Alex Benn=C3=A9e Virtualisation Tech Lead @ Linaro