From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 52A24CA0FED for ; Wed, 27 Aug 2025 18:38:19 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 064DE10E0FA; Wed, 27 Aug 2025 18:38:19 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="X9BIqebi"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.9]) by gabe.freedesktop.org (Postfix) with ESMTPS id 77C8210E0FA for ; Wed, 27 Aug 2025 18:38:17 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1756319897; x=1787855897; h=date:message-id:from:to:cc:subject:in-reply-to: references:mime-version; bh=ZgB3RAXLNPRYVR0Y2DIHKyHgOJUVgCPM82OvF7PuLkM=; b=X9BIqebiUTEPcMXJdAviuWb71eWxQWa+WFHoBmZlN4g5DU4eDGjCBCMk vCok8nNS6NT0czZEzzKn886uu7Ka5HSs6v4T4XG6GtBavqjnIvOsaFdnv Ykvd+c9TBGmDzBi+9JyB823T+7FWhf0MKkoUNIiwwvl7udHhyQ2NdG6Ud /1nNjWdL2tL9A075wBH2Mx0eaR7gLE4QdXJ8GTMmG4aDCECMQ2FHNuCAo 7zSw3Pg7r4lTubtZdUf2b2HkfzJ7QGmOqUkeoLVx/IFshyewYZMEkA9zL xcRGILLpbIQmHiiyAOLMJCHdgL+k8wIJa88cI/PXmo2kTktZmu+plIWrd A==; X-CSE-ConnectionGUID: zgNF3b8ORlqhXvNc+DT/sw== X-CSE-MsgGUID: oe9U/798S+mPXBf2JSM+JA== X-IronPort-AV: E=McAfee;i="6800,10657,11535"; a="69293224" X-IronPort-AV: E=Sophos;i="6.18,217,1751266800"; d="scan'208";a="69293224" Received: from fmviesa003.fm.intel.com ([10.60.135.143]) by fmvoesa103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Aug 2025 11:38:17 -0700 X-CSE-ConnectionGUID: IOyQwZ44Q/CBe0H92U19hg== X-CSE-MsgGUID: ILgBETDgSMitUbFZe8M6jg== X-ExtLoop1: 1 Received: from lmansuet-mobl.amr.corp.intel.com (HELO adixit-MOBL3.intel.com) ([10.125.87.18]) by fmviesa003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Aug 2025 11:38:17 -0700 Date: Wed, 27 Aug 2025 11:38:15 -0700 Message-ID: <87cy8gmwyw.wl-ashutosh.dixit@intel.com> From: "Dixit, Ashutosh" To: Umesh Nerlige Ramappa Cc: Subject: Re: [PATCH i-g-t v2 3/4] tests/intel/xe_oa: Add a test for tail address wrap In-Reply-To: <20250826224256.510692-9-umesh.nerlige.ramappa@intel.com> References: <20250826224256.510692-6-umesh.nerlige.ramappa@intel.com> <20250826224256.510692-9-umesh.nerlige.ramappa@intel.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?ISO-8859-4?Q?Goj=F2?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/29.4 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-BeenThere: igt-dev@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Development mailing list for IGT GPU Tools List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: igt-dev-bounces@lists.freedesktop.org Sender: "igt-dev" On Tue, 26 Aug 2025 15:43:00 -0700, Umesh Nerlige Ramappa wrote: > > Add a test to verify that the HW wraps to start of the OA buffer when a > report does not fit in the remaining space in the buffer. > > v2: > - Make test more robust > > Signed-off-by: Umesh Nerlige Ramappa > --- > tests/intel/xe_oa.c | 97 +++++++++++++++++++++++++++++++++++++++++++++ > 1 file changed, 97 insertions(+) > > diff --git a/tests/intel/xe_oa.c b/tests/intel/xe_oa.c > index d10ef00d6abc..24442e4b83c6 100644 > --- a/tests/intel/xe_oa.c > +++ b/tests/intel/xe_oa.c > @@ -4537,6 +4537,95 @@ static void closed_fd_and_unmapped_access(const struct drm_xe_engine_class_insta > try_invalid_access(vaddr); > } > > +static void read_reports(int fd, uint8_t *buf, size_t size) > +{ > + int len, total = 0; > + > + while (total < size) { > + len = read(fd, &buf[total], size - total); > + if (len == -1 && (errno == EIO || errno == EINTR)) > + continue; > + > + igt_assert(len); > + total += len; > + } > +} > + > +/** > + * SUBTEST: tail-address-wrap > + * Description: Test tail address wrap on odd format sizes. Ensure that the > + * format size is not a power of 2. This means that the last report will not be > + * broken down across the OA buffer end. Instead it will be written to the > + * beginning of the OA buffer. We will check the end of the buffer to ensure it > + * has zeroes in it. > + */ > +static void > +test_tail_address_wrap(const struct drm_xe_engine_class_instance *hwe, size_t oa_buffer_size) > +{ > + struct intel_xe_perf_metric_set *test_set = metric_set(hwe); > + uint64_t exponent = max_oa_exponent_for_period_lte(20000); > + uint64_t buffer_size = oa_buffer_size ?: buffer_fill_size; We are providing oa_buffer_size in the caller, so maybe can just use oa_buffer_size? But otherwise ok to leave as is too. > + uint64_t fmt = test_set->perf_oa_format; > + uint64_t properties[] = { > + DRM_XE_OA_PROPERTY_OA_UNIT_ID, 0, > + DRM_XE_OA_PROPERTY_SAMPLE_OA, true, > + DRM_XE_OA_PROPERTY_OA_METRIC_SET, test_set->perf_oa_metrics_set, > + DRM_XE_OA_PROPERTY_OA_FORMAT, __ff(fmt), > + DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT, exponent, > + DRM_XE_OA_PROPERTY_OA_ENGINE_INSTANCE, hwe->engine_instance, > + DRM_XE_OA_PROPERTY_OA_BUFFER_SIZE, buffer_size, > + DRM_XE_OA_PROPERTY_OA_DISABLED, true, > + }; > + struct intel_xe_oa_open_prop param = { > + .num_properties = ARRAY_SIZE(properties) / 2, > + .properties_ptr = to_user_pointer(properties), > + }; > + uint32_t fmt_size = get_oa_format(fmt).size; > + uint32_t fit_reports = buffer_size / fmt_size; > + uint32_t extra_reports = 10; > + uint32_t total_reports = fit_reports + extra_reports; > + uint32_t total_size = total_reports * fmt_size; > + uint8_t *buf = malloc(total_size); > + > + uint32_t wrap_offset = (fit_reports * fmt_size) >> 2; > + uint32_t end_offset = buffer_size >> 2; > + uint32_t *zero_area, *buffer_end, *buffer_start; You can just use u32, instead of the longer uint32_t, for these... > + int i; > + > + /* Ensure report does not fit */ This comment needs to be more specific, or just drop it. > + igt_require(wrap_offset < end_offset); > + > + stream_fd = __perf_open(drm_fd, ¶m, false); > + > + /* Read fit_reports + extra_reports */ > + do_ioctl(stream_fd, DRM_XE_OBSERVATION_IOCTL_ENABLE, 0); > + read_reports(stream_fd, buf, total_size); > + do_ioctl(stream_fd, DRM_XE_OBSERVATION_IOCTL_DISABLE, 0); > + > + /* Quick check for valid reports */ > + for (i = 0; i < total_reports; i++) { > + uint32_t *report = (uint32_t *)&buf[i * fmt_size]; > + > + igt_assert(report_reason(report) && oa_timestamp(report, fmt)); > + } > + > + /* mmap the buffer and check that the end of the buffer has zeroes */ > + buffer_start = mmap(0, buffer_size, PROT_READ, MAP_PRIVATE, stream_fd, 0); > + igt_assert(buffer_start); > + > + zero_area = buffer_start + wrap_offset; > + buffer_end = buffer_start + end_offset; > + > + /* Ensure HW did not write to this area */ > + while (zero_area < buffer_end) > + igt_assert_eq(*zero_area++, 0); > + > + munmap(buffer_start, buffer_size); > + > + __perf_close(stream_fd); > + free(buf); > +} > + > /** > * SUBTEST: map-oa-buffer > * Description: Verify mapping of oa buffer > @@ -5095,6 +5184,14 @@ igt_main > closed_fd_and_unmapped_access(hwe); > } > > + igt_subtest_with_dynamic("tail-address-wrap") { > + long k = random() % num_buf_sizes; > + > + igt_require(oau->capabilities & DRM_XE_OA_CAPS_OA_BUFFER_SIZE); > + __for_one_hwe_in_oag_w_arg(hwe, buf_sizes[k].name) > + test_tail_address_wrap(hwe, buf_sizes[k].size); > + } > + > igt_subtest_group { > igt_fixture { > perf_init_whitelist(); Otherwise, this is also: Reviewed-by: Ashutosh Dixit