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bh=HzrQ8UsauV0uUlBYYQNKljD4+gLMnEGKsLGyhjx5bAE=; b=2QYZ761sM6UEzTwDs7IDwJ1Mhr0mMkKFYPkGknyM6LPizE1YHI2TEhcVYBPBlHRTbwspo5 j0ypVgVv0Jv974DCPhBwnI337qtdAFX/8FvCZWCYRy+AKPVoMdAmrxxTwHSPTI7TfucYGi oMx5z/qpOCYEXcWSNO5CLDufO36f6MCz5JZvgtTIkuoxhqNoZNOqFBZLhrd9XIEz6rC6oL fFuNyF3jm7jitetwI+KSz4Xb3lYvjk4KtJz6J3ERyswHNkTpe2KhEULFRwcCxMCe5Fuhv3 HlMCJzMOG40NdhBM6H+RIxCxVrDrc5X3CagXUQXyEOQm3I8gaM+uU5bZJkqX6Q== From: Miquel Raynal To: Mark Brown Cc: Santhosh Kumar K , richard@nod.at, vigneshr@ti.com, tudor.ambarus@linaro.org, pratyush@kernel.org, mwalle@kernel.org, p-mantena@ti.com, linux-spi@vger.kernel.org, linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org, a-dutta@ti.com, u-kumar1@ti.com, praneeth@ti.com Subject: Re: [RFC PATCH 01/10] spi: spi-mem: Introduce support for tuning controller In-Reply-To: <6c35baad-a332-4b0a-96ca-1cdb3840ad94@sirena.org.uk> (Mark Brown's message of "Wed, 13 Aug 2025 21:26:06 +0100") References: <20250811193219.731851-1-s-k6@ti.com> <20250811193219.731851-2-s-k6@ti.com> <6c35baad-a332-4b0a-96ca-1cdb3840ad94@sirena.org.uk> User-Agent: mu4e 1.12.7; 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arc=none smtp.client-ip=185.246.85.4 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="2QYZ761s" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-03.galae.net (Postfix) with ESMTPS id 9B76A4E40C29; Sun, 24 Aug 2025 17:03:13 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id 558BB605F1; Sun, 24 Aug 2025 17:03:13 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 9145F1C228A5B; Sun, 24 Aug 2025 19:02:57 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1756054990; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=HzrQ8UsauV0uUlBYYQNKljD4+gLMnEGKsLGyhjx5bAE=; b=2QYZ761sM6UEzTwDs7IDwJ1Mhr0mMkKFYPkGknyM6LPizE1YHI2TEhcVYBPBlHRTbwspo5 j0ypVgVv0Jv974DCPhBwnI337qtdAFX/8FvCZWCYRy+AKPVoMdAmrxxTwHSPTI7TfucYGi oMx5z/qpOCYEXcWSNO5CLDufO36f6MCz5JZvgtTIkuoxhqNoZNOqFBZLhrd9XIEz6rC6oL fFuNyF3jm7jitetwI+KSz4Xb3lYvjk4KtJz6J3ERyswHNkTpe2KhEULFRwcCxMCe5Fuhv3 HlMCJzMOG40NdhBM6H+RIxCxVrDrc5X3CagXUQXyEOQm3I8gaM+uU5bZJkqX6Q== From: Miquel Raynal To: Mark Brown Cc: Santhosh Kumar K , richard@nod.at, vigneshr@ti.com, tudor.ambarus@linaro.org, pratyush@kernel.org, mwalle@kernel.org, p-mantena@ti.com, linux-spi@vger.kernel.org, linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org, a-dutta@ti.com, u-kumar1@ti.com, praneeth@ti.com Subject: Re: [RFC PATCH 01/10] spi: spi-mem: Introduce support for tuning controller In-Reply-To: <6c35baad-a332-4b0a-96ca-1cdb3840ad94@sirena.org.uk> (Mark Brown's message of "Wed, 13 Aug 2025 21:26:06 +0100") References: <20250811193219.731851-1-s-k6@ti.com> <20250811193219.731851-2-s-k6@ti.com> <6c35baad-a332-4b0a-96ca-1cdb3840ad94@sirena.org.uk> User-Agent: mu4e 1.12.7; emacs 30.1 Date: Sun, 24 Aug 2025 19:02:56 +0200 Message-ID: <87cy8khcu7.fsf@bootlin.com> Precedence: bulk X-Mailing-List: linux-spi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable X-Last-TLS-Session-Version: TLSv1.3 Hello, On 13/08/2025 at 21:26:06 +01, Mark Brown wrote: > On Tue, Aug 12, 2025 at 01:02:10AM +0530, Santhosh Kumar K wrote: >> From: Pratyush Yadav >>=20 >> Some controllers like the Cadence OSPI controller need to perform a >> tuning sequence to operate at high data rates. Tuning is needs to happen >> once the device is switched to appropriate mode (say 8S-8S-8S or >> 8D-8D-8D). Add a hook that spi-mem client devices can call in order to t= une >> the controller to operate in a given mode and data rate. >>=20 >> This is somewhat similar to eMMC/SD tuning for higher speed modes like >> HS200, but there isn't a standard specification around the same though. > > Should we have something that blocks these tuning required modes without > the appropriate tuning, and/or allows discovery of which modes require > this tuning? This all feels very landmineish - client drivers just have > to know when tuning is required. The maximum bus frequency will tell whether tuning is relevant or not I guess. In the case of the Cadence controller, the bus speed is key to determine whether calibration should happen or not because when PHY calibration is enabled, the SPI bus frequency is equal to the controller clock rate (pre-scalers are bypassed). So the criteria for enabling calibration is: max SPI bus freq >=3D min controller clock rate Thanks, Miqu=C3=A8l