From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 53FAA3597E for ; Sun, 22 Jun 2025 08:39:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750581593; cv=none; b=qIufx5Cci85N+VAgIq49C8PuCxTnrBtfPFBoJfsgJB0ZBs9DnUK14dLWYFo8oci2MkUiL6mGS6R0eCCpb34hgc+FhVvYZNfrVSspkJkErYmYZuw4NJ1N6pI0+4JPHUoUAsWiIVwhXmlT5rglKq70m8Iqjq8/1NC/aCs86IMwndw= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750581593; c=relaxed/simple; bh=DVYkLF5dA8i0pfLGB/1f6MWOMREtNvojBTWbzvce0oo=; h=Date:Message-ID:From:To:Cc:Subject:In-Reply-To:References: MIME-Version:Content-Type; b=DGGZIR6RPIeK01LrHUNQWb79OOuVMFA/H9KP9v4qt52NVsGZ6K8pyFeTvOOlsMdSmFlO981iQUGX7Gp9VKfl118ov6xt47w0RmFWcH+E0GrBaRpL4gEtYSRgcy7S8JzhrQ4zBNwECvaUcePDM1JHhjaPwXFyZgc57VHT0DV3Dik= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=uSQB7vBi; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="uSQB7vBi" Received: by smtp.kernel.org (Postfix) with ESMTPSA id D045CC4CEE3; Sun, 22 Jun 2025 08:39:52 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1750581592; bh=DVYkLF5dA8i0pfLGB/1f6MWOMREtNvojBTWbzvce0oo=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=uSQB7vBiXzuG0cUEgk9C8CDqLcnizfkQLmVFwCmSkSePb7oyegwD9Z7n4CEEboxjN 68ndp+mu2i4dFUrwyUJV2Cn+Qy5Bt7Kxr864wf1vCS2SiGtXUN1U3wvt0XKmhPGZxb 7O9Df8MhRN5nHy8CWlMfIRwKsrwlBYnKlmohKxfSZXf1NSINpWs0WseDuj3nHbvnjK aUKORZ+IxG4b8D3MfK1JJ4HwIoE+e5RW4O03ZX7W3WKtbk0/EvPLIw6GYg4MEoCIYt rVpeER7elnKoPkkK2OFDakardEgOP0n4Kj/ETxiMhSrGSXBxIeLdFWFBjiAnu3yj7Q vNuIcxO1UPYZw== Received: from sofa.misterjones.org ([185.219.108.64] helo=lobster-girl.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.95) (envelope-from ) id 1uTGEw-008wJ6-Dx; Sun, 22 Jun 2025 09:39:50 +0100 Date: Sun, 22 Jun 2025 09:39:50 +0100 Message-ID: <87cyawf9ux.wl-maz@kernel.org> From: Marc Zyngier To: Oliver Upton Cc: kvmarm@lists.linux.dev, Joey Gouly , Suzuki K Poulose , Zenghui Yu Subject: Re: [PATCH v2 19/27] KVM: arm64: Take "masked" SEAs to EL2 when TMEA is set In-Reply-To: <20250616230308.1192565-20-oliver.upton@linux.dev> References: <20250616230308.1192565-1-oliver.upton@linux.dev> <20250616230308.1192565-20-oliver.upton@linux.dev> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/30.1 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) Precedence: bulk X-Mailing-List: kvmarm@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: oliver.upton@linux.dev, kvmarm@lists.linux.dev, joey.gouly@arm.com, suzuki.poulose@arm.com, yuzenghui@huawei.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false On Tue, 17 Jun 2025 00:03:00 +0100, Oliver Upton wrote: > > SEAs can never actually be masked (they're synchronous after all), but > the value of PSTATE.A used as a proxy for whether software might be in > the middle of an SEA handler. And, when TMEA is set, these "masked" SEAs > are actually routed to EL2. > > Signed-off-by: Oliver Upton > --- > arch/arm64/kvm/inject_fault.c | 9 ++++++++- > 1 file changed, 8 insertions(+), 1 deletion(-) > > diff --git a/arch/arm64/kvm/inject_fault.c b/arch/arm64/kvm/inject_fault.c > index e689002f10b6..3eab7690c54e 100644 > --- a/arch/arm64/kvm/inject_fault.c > +++ b/arch/arm64/kvm/inject_fault.c > @@ -209,7 +209,14 @@ static void __kvm_inject_sea(struct kvm_vcpu *vcpu, bool iabt, u64 addr) > > static bool kvm_sea_target_is_el2(struct kvm_vcpu *vcpu) > { > - return __vcpu_sys_reg(vcpu, HCR_EL2) & (HCR_TGE | HCR_TEA); > + if (__vcpu_sys_reg(vcpu, HCR_EL2) & (HCR_TGE | HCR_TEA)) > + return true; > + > + if (!vcpu_mode_priv(vcpu)) > + return false; > + > + return (*vcpu_cpsr(vcpu) & PSR_A_BIT) && > + (__vcpu_sys_reg(vcpu, HCRX_EL2) & HCRX_EL2_TMEA); > } > > int kvm_inject_sea(struct kvm_vcpu *vcpu, bool iabt, u64 addr) Only tangentially related to this patch and the previous one: what should a hypervisor do when inheriting an SEA/SError from its guest? I can't see a good way to handle that other than either terminating the guest, or ignoring the problem altogether. But maybe that's what the design point is (eyes roll...). M. -- Jazz isn't dead. It just smells funny.