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Fri, 20 Dec 2024 11:17:11 -0500 X-MC-Unique: inbgGH3gNGycdQ_GQQdWKQ-1 X-Mimecast-MFC-AGG-ID: inbgGH3gNGycdQ_GQQdWKQ Received: from mx-prod-int-05.mail-002.prod.us-west-2.aws.redhat.com (mx-prod-int-05.mail-002.prod.us-west-2.aws.redhat.com [10.30.177.17]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by mx-prod-mc-05.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTPS id E32571944D32; Fri, 20 Dec 2024 16:17:07 +0000 (UTC) Received: from localhost (dhcp-192-244.str.redhat.com [10.33.192.244]) by mx-prod-int-05.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTPS id 661581956053; Fri, 20 Dec 2024 16:17:05 +0000 (UTC) From: Cornelia Huck To: Kashyap Chamarthy , Marc Zyngier Cc: Eric Auger , Daniel =?utf-8?Q?P=2E_Berrang?= =?utf-8?Q?=C3=A9?= , eric.auger.pro@gmail.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, kvmarm@lists.linux.dev, peter.maydell@linaro.org, richard.henderson@linaro.org, alex.bennee@linaro.org, oliver.upton@linux.dev, sebott@redhat.com, shameerali.kolothum.thodi@huawei.com, armbru@redhat.com, abologna@redhat.com, jdenemar@redhat.com, shahuang@redhat.com, mark.rutland@arm.com, philmd@linaro.org, pbonzini@redhat.com Subject: Re: [PATCH RFCv2 00/20] kvm/arm: Introduce a customizable aarch64 KVM host model In-Reply-To: Organization: "Red Hat GmbH, Sitz: Werner-von-Siemens-Ring 12, D-85630 Grasbrunn, Handelsregister: Amtsgericht =?utf-8?Q?M=C3=BCnchen=2C?= HRB 153243, =?utf-8?Q?Gesch=C3=A4ftsf=C3=BChrer=3A?= Ryan Barnhart, Charles Cachera, Michael O'Neill, Amy Ross" References: <20241206112213.88394-1-cohuck@redhat.com> <8734it1bv6.fsf@redhat.com> <1fea79e4-7a31-4592-8495-7b18cd82d02b@redhat.com> <8634ijrh8q.wl-maz@kernel.org> <86zfkrptmj.wl-maz@kernel.org> User-Agent: Notmuch/0.38.3 (https://notmuchmail.org) Date: Fri, 20 Dec 2024 17:17:02 +0100 Message-ID: <87cyhmba81.fsf@redhat.com> Precedence: bulk X-Mailing-List: kvmarm@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain X-Scanned-By: MIMEDefang 3.0 on 10.30.177.17 On Fri, Dec 20 2024, Kashyap Chamarthy wrote: > Related tangent on CPU feature discoverability on ARM: > > Speaking of "Neoverse-N1", looking at a system that I have access to, > the `lscpu` output does not say anything about who the integrator is; it > only says: > > ... > Vendor ID: ARM > Model name: Neoverse-N1 > ... > > I realize, `lscpu` displays only whatever the kernel knows. Nothing in > `dmidecode` either. > > Also, it looks like there's no equivalent of a "CPUID" instruction (I > realize it is x86-specific) on ARM. Although, I came across a Google > Git repo that seems to implement a bespoke, "aarch64_cpuid". From a > what I see, it seems to fetch the "Main ID Register" (MIDR_EL1) - I > don't know enough about it to understand its implications: > > https://github.com/google/cpu_features/blob/main/src/impl_aarch64_cpuid.c My guess is that this is mostly for "we have code that looks for a cpuid like on x86, let's provide some code on arm that gives something that is at least somewhat useful." For "CPU feature discoverability", I don't think that there's any way other than looking at the actual id registers. It would be nice if you could at least know that "there are some differences in features" by comparing MIDR/REVIDR/AIDR, but that's not the case IIRC? [Anyway, I'm off for the year :)]