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Fri, 13 Dec 2024 21:09:49 +0000 From: Fabiano Rosas To: Nabih Estefan , peter.maydell@linaro.org Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org, lvivier@redhat.com, pbonzini@redhat.com, roqueh@google.com, venture@google.com, Nabih Estefan Subject: Re: [PATCH] tests/qtest/sse-timer-test: Add watchdog reset to sse-timer test In-Reply-To: <20241213002602.4181289-1-nabihestefan@google.com> References: <20241213002602.4181289-1-nabihestefan@google.com> Date: Fri, 13 Dec 2024 18:09:47 -0300 Message-ID: <87cyhvxpb8.fsf@suse.de> MIME-Version: 1.0 Content-Type: text/plain X-Rspamd-Queue-Id: 1224E1F394 X-Spamd-Result: default: False [-4.51 / 50.00]; BAYES_HAM(-3.00)[100.00%]; NEURAL_HAM_LONG(-1.00)[-1.000]; R_DKIM_ALLOW(-0.20)[suse.de:s=susede2_rsa,suse.de:s=susede2_ed25519]; NEURAL_HAM_SHORT(-0.20)[-0.999]; MIME_GOOD(-0.10)[text/plain]; MX_GOOD(-0.01)[]; RCPT_COUNT_SEVEN(0.00)[9]; RCVD_VIA_SMTP_AUTH(0.00)[]; MISSING_XM_UA(0.00)[]; MIME_TRACE(0.00)[0:+]; ARC_NA(0.00)[]; MID_RHS_MATCH_FROM(0.00)[]; RCVD_TLS_ALL(0.00)[]; TO_DN_SOME(0.00)[]; FROM_EQ_ENVFROM(0.00)[]; FROM_HAS_DN(0.00)[]; FUZZY_BLOCKED(0.00)[rspamd.com]; RCVD_COUNT_TWO(0.00)[2]; DKIM_SIGNED(0.00)[suse.de:s=susede2_rsa,suse.de:s=susede2_ed25519]; TO_MATCH_ENVRCPT_ALL(0.00)[]; DKIM_TRACE(0.00)[suse.de:+] X-Rspamd-Server: rspamd2.dmz-prg2.suse.org X-Rspamd-Action: no action X-Spam-Score: -4.51 Received-SPF: pass client-ip=2a07:de40:b251:101:10:150:64:2; envelope-from=farosas@suse.de; helo=smtp-out2.suse.de X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-arm-bounces+alex.bennee=linaro.org@nongnu.org Sender: qemu-arm-bounces+alex.bennee=linaro.org@nongnu.org X-TUID: EZj38i1KPlf5 Nabih Estefan writes: > Recent CDMSK Watchdog changes (eff9dc5660fad3a610171c56a5ec3fada245e519) > updated the CDMSK APB Watchdog to not free run out of reset. That led to > this test failing since it never triggers the watchdog to start running. > No watchdog running means that the timer and counter in the test cannot > start, leading to failures in the assert statements throughout the test. > Adding a reset and enable of the watchdog to the reset function solves > this problem by enabling the watchdog and thus letting the timer and > counter run as expected > > Also renaming the reset_counter_and_timer function since it now also > affects the watchdog. > > To reproduce the failure at HEAD: > ./configure --target-list=arm-softmmu > make -j check-report-qtest-arm.junit.xml > > Signed-off-by: Nabih Estefan > --- > scripts/meson-buildoptions.sh.tmp | 0 > tests/qtest/sse-timer-test.c | 19 ++++++++++++++----- > 2 files changed, 14 insertions(+), 5 deletions(-) > create mode 100644 scripts/meson-buildoptions.sh.tmp > > diff --git a/scripts/meson-buildoptions.sh.tmp b/scripts/meson-buildoptions.sh.tmp > new file mode 100644 > index 0000000000..e69de29bb2 By the way, there's an extra file being created here that we don't want. > diff --git a/tests/qtest/sse-timer-test.c b/tests/qtest/sse-timer-test.c > index fd5635d4c9..d7a53ac23a 100644 > --- a/tests/qtest/sse-timer-test.c > +++ b/tests/qtest/sse-timer-test.c > @@ -29,6 +29,13 @@ > /* Base of the System Counter control frame */ > #define COUNTER_BASE 0x58100000 > > +/* Base of the MSSDK APB Watchdog Device */ > +#define WDOG_BASE 0x4802e000 > + > +/* CMSDK Watchdog offsets */ > +#define WDOGLOAD 0 > +#define WDOGCONTROL 8 > + > /* SSE counter register offsets in the control frame */ > #define CNTCR 0 > #define CNTSR 0x4 > @@ -63,24 +70,26 @@ static void clock_step_ticks(uint64_t ticks) > clock_step(FOUR_TICKS * (ticks >> 2)); > } > > -static void reset_counter_and_timer(void) > +static void reset_watchdog_counter_and_timer(void) > { > /* > - * Reset the system counter and the timer between tests. This > + * Reset the system watchdog, counter and the timer between tests. This > * isn't a full reset, but it's sufficient for what the tests check. > */ > + writel(WDOG_BASE + WDOGCONTROL, 0); > writel(COUNTER_BASE + CNTCR, 0); > writel(TIMER_BASE + CNTP_CTL, 0); > writel(TIMER_BASE + CNTP_AIVAL_CTL, 0); > writel(COUNTER_BASE + CNTCV_LO, 0); > writel(COUNTER_BASE + CNTCV_HI, 0); > + writel(WDOG_BASE + WDOGCONTROL, 1); > } > > static void test_counter(void) > { > /* Basic counter functionality test */ > > - reset_counter_and_timer(); > + reset_watchdog_counter_and_timer(); > /* The counter should start disabled: check that it doesn't move */ > clock_step_ticks(100); > g_assert_cmpuint(readl(COUNTER_BASE + CNTCV_LO), ==, 0); > @@ -103,7 +112,7 @@ static void test_timer(void) > { > /* Basic timer functionality test */ > > - reset_counter_and_timer(); > + reset_watchdog_counter_and_timer(); > /* > * The timer is behind a Peripheral Protection Controller, and > * qtest accesses are always non-secure (no memory attributes), > @@ -195,7 +204,7 @@ static void test_timer_scale_change(void) > * Test that the timer responds correctly to counter > * scaling changes while it has an active timer. > */ > - reset_counter_and_timer(); > + reset_watchdog_counter_and_timer(); > /* Give ourselves access to the timer, and enable the counter and timer */ > writel(PERIPHNSPPC0, 1); > writel(COUNTER_BASE + CNTCR, 1);