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Tue, 12 Mar 2024 06:25:00 -0700 (PDT) Received: from draig (localhost [IPv6:::1]) by draig.lan (Postfix) with ESMTP id A239B5F7D9; Tue, 12 Mar 2024 13:24:59 +0000 (GMT) From: =?utf-8?Q?Alex_Benn=C3=A9e?= To: Nicholas Piggin Cc: qemu-devel@nongnu.org, Pavel Dovgalyuk , Philippe =?utf-8?Q?Mathieu-Daud=C3=A9?= , Richard Henderson , Paolo Bonzini , John Snow , Cleber Rosa , Wainer dos Santos Moschetta , Beraldo Leal , Michael Tokarev , qemu-ppc@nongnu.org Subject: Re: [PATCH v4 22/24] target/ppc: fix timebase register reset state In-Reply-To: <20240311174026.2177152-23-npiggin@gmail.com> (Nicholas Piggin's message of "Tue, 12 Mar 2024 03:40:24 +1000") References: <20240311174026.2177152-1-npiggin@gmail.com> <20240311174026.2177152-23-npiggin@gmail.com> User-Agent: mu4e 1.12.1; emacs 29.1 Date: Tue, 12 Mar 2024 13:24:59 +0000 Message-ID: <87cyrzpopg.fsf@draig.linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2a00:1450:4864:20::530; envelope-from=alex.bennee@linaro.org; helo=mail-ed1-x530.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Nicholas Piggin writes: > (H)DEC and PURR get reset before icount does, which causes them to be > skewed and not match the init state. This can cause replay to not > match the recorded trace exactly. For DEC and HDEC this is usually not > noticable since they tend to get programmed before affecting the > target machine. PURR has been observed to cause replay bugs when > running Linux. > > Fix this by resetting using a time of 0. > > Cc: qemu-ppc@nongnu.org > Signed-off-by: Nicholas Piggin > --- > hw/ppc/ppc.c | 11 ++++++++--- > target/ppc/machine.c | 4 ++++ > 2 files changed, 12 insertions(+), 3 deletions(-) > > diff --git a/hw/ppc/ppc.c b/hw/ppc/ppc.c > index fadb8f5239..f22321779e 100644 > --- a/hw/ppc/ppc.c > +++ b/hw/ppc/ppc.c > @@ -1112,16 +1112,21 @@ void cpu_ppc_tb_reset(CPUPPCState *env) > timer_del(tb_env->hdecr_timer); > ppc_set_irq(cpu, PPC_INTERRUPT_HDECR, 0); > tb_env->hdecr_next =3D 0; > + _cpu_ppc_store_hdecr(cpu, 0, 0, 0, 64); > } >=20=20 > /* > * There is a bug in Linux 2.4 kernels: > * if a decrementer exception is pending when it enables msr_ee at s= tartup, > * it's not ready to handle it... > + * > + * On machine reset, in this is called before icount is reset, so > + * for icount-mode, setting TB registers using now=3Dqemu_clock_get_= ns > + * results in them being skewed when icount does get reset. Use an > + * explicit 0 to get a consistent reset state. > */ > - cpu_ppc_store_decr(env, -1); > - cpu_ppc_store_hdecr(env, -1); > - cpu_ppc_store_purr(env, 0x0000000000000000ULL); > + _cpu_ppc_store_decr(cpu, 0, 0, -1, 64); > + _cpu_ppc_store_purr(env, 0, 0); > } >=20=20 > void cpu_ppc_tb_free(CPUPPCState *env) > diff --git a/target/ppc/machine.c b/target/ppc/machine.c > index 203fe28e01..4c4294eafe 100644 > --- a/target/ppc/machine.c > +++ b/target/ppc/machine.c > @@ -215,6 +215,8 @@ static int cpu_pre_save(void *opaque) > * it here. > */ > env->spr[SPR_DECR] =3D cpu_ppc_load_decr(env); > + printf("cpu_ppc_pre_save TB:0x%016lx\n", cpu_ppc_load_tbl(env)); > + printf("cpu_ppc_pre_save DEC:0x%016lx\n", > cpu_ppc_load_decr(env)); I think this is left over debug, which btw needs proper types: ../../target/ppc/machine.c: In function =E2=80=98cpu_pre_save=E2=80=99: ../../target/ppc/machine.c:219:45: error: format =E2=80=98%lx=E2=80=99 ex= pects argument of type =E2=80=98long unsigned int=E2=80=99, but argument 2 = has type =E2=80=98target_ulong=E2=80=99 {aka =E2=80=98unsigned int=E2=80=99= } [-Werror=3Dformat=3D] 219 | printf("cpu_ppc_pre_save DEC:0x%016lx\n", cpu_ppc_load_de= cr(env)); | ~~~~~^ ~~~~~~~~~~~~~~~= ~~~~~~~ | | | | | target_ulong {a= ka unsigned int} | long unsigned int | %016x ../../target/ppc/machine.c: In function =E2=80=98cpu_post_load=E2=80=99: ../../target/ppc/machine.c:339:45: error: format =E2=80=98%lx=E2=80=99 ex= pects argument of type =E2=80=98long unsigned int=E2=80=99, but argument 2 = has type =E2=80=98target_ulong=E2=80=99 {aka =E2=80=98unsigned int=E2=80=99= } [-Werror=3Dformat=3D] 339 | printf("cpu_ppc_post_ld DEC:0x%016lx\n", cpu_ppc_load_de= cr(env)); | ~~~~~^ ~~~~~~~~~~~~~~~= ~~~~~~~ | | | | | target_ulong {a= ka unsigned int} | long unsigned int | %016x cc1: all warnings being treated as errors > } >=20=20 > return 0; > @@ -333,6 +335,8 @@ static int cpu_post_load(void *opaque, int version_id) > * triggered types (including HDEC) would need to carry more sta= te. > */ > cpu_ppc_store_decr(env, env->spr[SPR_DECR]); > + printf("cpu_ppc_post_ld TB:0x%016lx\n", cpu_ppc_load_tbl(env)); > + printf("cpu_ppc_post_ld DEC:0x%016lx\n", cpu_ppc_load_decr(env)= ); > pmu_mmcr01_updated(env); > } --=20 Alex Benn=C3=A9e Virtualisation Tech Lead @ Linaro