[PATCH] x86/smpboot/64: Handle X2APIC BIOS inconsistency gracefully

[Thomas Gleixner <tglx@linutronix.de>]

Chris reported that a Dell PowerEdge T340 system stopped to boot when
upgrading to a kernel which contains the parallel hotplug changes.
Disabling parallel hotplug on the kernel command line makes it boot again.

It turns out that the Dell BIOS has x2APIC enabled and the boot CPU comes
up in X2APIC mode, but the APs come up inconsistently in xAPIC mode.

Parallel hotplug requires that the upcoming CPU reads out its APIC ID from
the local APIC in order to map it to the Linux CPU number.

In this particular case the readout on the APs uses the MMIO mapped
registers because the BIOS failed to enable x2APIC mode. That readout
results in a pagefault because the kernel does not have the APIC MMIO space
mapped when X2APIC mode was enabled by the BIOS on the boot CPU and the
kernel switched to X2APIC mode early. That page fault can't be handled on
the upcoming CPU that early and results in a silent boot failure.

If parallel hotplug is disabled the system boots because in that case
the APIC ID read is not required as the Linux CPU number is provided to
the AP in the smpboot control word. When the kernel uses x2APIC mode
then the APs are switched to x2APIC mode too slightly later in the
bringup process, but there is no reason to do it that late.

Cure the BIOS bogosity by checking in the parallel bootup path whether the
kernel uses x2APIC mode and if so switching over the APs to x2APIC mode
before the APIC ID readout.

Fixes: 0c7ffa32dbd6 "x86/smpboot/64: Implement arch_cpuhp_init_parallel_bringup() and enable it"
Reported-by: Chris Lindee <chris.lindee@gmail.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Tested-by: Chris Lindee <chris.lindee@gmail.com>
Cc: stable@vger.kernel.org
---
 arch/x86/kernel/head_64.S |   16 ++++++++++++++++
 1 file changed, 16 insertions(+)

--- a/arch/x86/kernel/head_64.S
+++ b/arch/x86/kernel/head_64.S
@@ -268,6 +268,22 @@ SYM_INNER_LABEL(secondary_startup_64_no_
 	testl	$X2APIC_ENABLE, %eax
 	jnz	.Lread_apicid_msr
 
+#ifdef CONFIG_X86_X2APIC
+	/*
+	 * If system is in X2APIC mode then MMIO base mignt not be
+	 * mapped causing the MMIO read below to fault. Faults can't
+	 * be handled at that point.
+	 */
+	cmpl	$0, x2apic_mode(%rip)
+	jz	.Lread_apicid_mmio
+
+	/* Force the AP into X2APIC mode. */
+	orl	$X2APIC_ENABLE, %eax
+	wrmsr
+	jmp	.Lread_apicid_msr
+#endif
+
+.Lread_apicid_mmio:
 	/* Read the APIC ID from the fix-mapped MMIO space. */
 	movq	apic_mmio_base(%rip), %rcx
 	addq	$APIC_ID, %rcx