From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C7135C433F5 for ; Thu, 26 May 2022 12:53:58 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Subject:Cc:To:From:Message-ID:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=DANhxRymaW4W4bHbaKiFre7g1f7hJtyaJprbZltU50g=; b=V7qCcyRympY4AS RJIcIuEOVYp3qlgcWMgsvrnS3JjlRwL9JFZQj+Xpwg+wi8ZLU91THstz4Was/Dzd8cl3z2EMgwZVN Y6oDaFsEIbz3oNFXDiiEEkfEHUa/ihbJkiPVELV9P8P9xebnyKB0eZlGMmM2Ldquip1ohGbX4mkfo DAulgjUnhqGZtzZPSZX/ZhFwH6j0z2/sHX3COos0TRIA/kRQtFTQGHiqlZi3AFg7C35ZTKpA8ushx lCGyl7759ZTDIfQGHPXMVUGRFCL1ASrUZ90KlLIVdk1NSgKivThUgnRNKlA6UnqaBW9EmAy4lXRVp OURjkFEqYGFxinM2ldMA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nuCyw-00EvHD-Vj; Thu, 26 May 2022 12:52:51 +0000 Received: from ams.source.kernel.org ([2604:1380:4601:e00::1]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1nuCyt-00EvGJ-Im for linux-arm-kernel@lists.infradead.org; Thu, 26 May 2022 12:52:49 +0000 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id 4970FB8204D; Thu, 26 May 2022 12:52:46 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id E6244C385A9; Thu, 26 May 2022 12:52:44 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1653569564; bh=Z3C6dkYdPm8lWq2xILiBEXeVjfcYz6sTr481QH2GFp4=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=YdFlNA8n+XGTjQ7ypalb4t9BC9Ib5TAVbONZ1gNnJ6QPJ51RnQw8NYxoRbM4P0sY6 Hiq5RTMPDLMRMWBht8+FYLqcl13WNd7eriPi/WK+O1CFtrgWv8KPUAeCl7J57aTLcx zLhjZqcZD5z954/dlKPhE0YKV+xi2H1Lfv4nTPZ2RbIOBFfRRnWTQq8b8aDdKQzvP2 73gR3/f5bsH3sGYVo+jKBUSUR5zC7FOnWfCEY6PHysCBZccqqELZBkdGUoBKXXu3pK Q4vNvS3MfESk3f7723cgVJ4lEr4XEBHQCyAwnCH79X5u2rs+3eR61ZtVf1TrTcD844 9dF8AtOxNq2WQ== Received: from athedsl-4557779.home.otenet.gr ([94.70.87.219] helo=wait-a-minute.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1nuCyo-00Dquf-Cp; Thu, 26 May 2022 13:52:42 +0100 Date: Thu, 26 May 2022 13:52:40 +0100 Message-ID: <87czg0mp5z.wl-maz@kernel.org> From: Marc Zyngier To: richard clark Cc: Robin Murphy , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, s32@nxp.com, leoyang.li@nxp.com, catalin-dan.udma@nxp.com, bogdan.hamciuc@nxp.com, bogdan.folea@nxp.com, ciprianmarian.costea@nxp.com, radu-nicolae.pirea@nxp.com, ghennadi.procopciuc@nxp.com Subject: Re: Question about SPIs' interrupt trigger type restrictions In-Reply-To: References: <35f95ba3-8a7b-7918-0f9d-e14274a5ffe9@arm.com> <87ee0gn5rq.wl-maz@kernel.org> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/27.1 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") X-SA-Exim-Connect-IP: 94.70.87.219 X-SA-Exim-Rcpt-To: richard.xnu.clark@gmail.com, robin.murphy@arm.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, s32@nxp.com, leoyang.li@nxp.com, catalin-dan.udma@nxp.com, bogdan.hamciuc@nxp.com, bogdan.folea@nxp.com, ciprianmarian.costea@nxp.com, radu-nicolae.pirea@nxp.com, ghennadi.procopciuc@nxp.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220526_055247_960459_624C70F6 X-CRM114-Status: GOOD ( 43.34 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org T24gVGh1LCAyNiBNYXkgMjAyMiAxMzowOTozMiArMDEwMCwKcmljaGFyZCBjbGFyayA8cmljaGFy ZC54bnUuY2xhcmtAZ21haWwuY29tPiB3cm90ZToKPiAKPiBDQydpbmcgc29tZSBueHAgZ3V5cyBm b3IgdGhlIFMzMkcyNzRBIFNPQy4uLgo+IAo+IE9uIFRodSwgTWF5IDI2LCAyMDIyIGF0IDI6NTQg UE0gTWFyYyBaeW5naWVyIDxtYXpAa2VybmVsLm9yZz4gd3JvdGU6Cj4gPgo+ID4gT24gVGh1LCAy NiBNYXkgMjAyMiAwNDo0NDo0MSArMDEwMCwKPiA+IHJpY2hhcmQgY2xhcmsgPHJpY2hhcmQueG51 LmNsYXJrQGdtYWlsLmNvbT4gd3JvdGU6Cj4gPiA+Cj4gPiA+IE9uIFRodSwgTWF5IDI2LCAyMDIy IGF0IDM6MTQgQU0gUm9iaW4gTXVycGh5IDxyb2Jpbi5tdXJwaHlAYXJtLmNvbT4gd3JvdGU6Cj4g PiA+ID4KPiA+ID4gPiBPbiAyMDIyLTA1LTI1IDExOjAxLCByaWNoYXJkIGNsYXJrIHdyb3RlOgo+ ID4gPiA+ID4gSGkgTWFyYywKPiA+ID4gPiA+Cj4gPiA+ID4gPiBGb3IgYmVsb3cgY29kZSBzbmlw cGV0IGFib3V0IFNQSSBpbnRlcnJ1cHQgdHJpZ2dlciB0eXBlOgo+ID4gPiA+ID4KPiA+ID4gPiA+ IHN0YXRpYyBpbnQgZ2ljX3NldF90eXBlKHN0cnVjdCBpcnFfZGF0YSAqZCwgdW5zaWduZWQgaW50 IHR5cGUpCj4gPiA+ID4gPiB7Cj4gPiA+ID4gPiAgICAgICAgICAuLi4KPiA+ID4gPiA+ICAgICAg ICAgIC8qIFNQSXMgaGF2ZSByZXN0cmljdGlvbnMgb24gdGhlIHN1cHBvcnRlZCB0eXBlcyAqLwo+ ID4gPiA+ID4gICAgICAgICAgaWYgKChyYW5nZSA9PSBTUElfUkFOR0UgfHwgcmFuZ2UgPT0gRVNQ SV9SQU5HRSkgJiYKPiA+ID4gPiA+ICAgICAgICAgICAgICB0eXBlICE9IElSUV9UWVBFX0xFVkVM X0hJR0ggJiYgdHlwZSAhPSBJUlFfVFlQRV9FREdFX1JJU0lORykKPiA+ID4gPiA+ICAgICAgICAg ICAgICAgICAgcmV0dXJuIC1FSU5WQUw7Cj4gPiA+ID4gPiAgICAgICAgICAuLi4KPiA+ID4gPiA+ IH0KPiA+ID4gPiA+Cj4gPiA+ID4gPiBXZSBoYXZlIGEgZGV2aWNlIGF0IGhhbmQgd2hvc2UgaW50 ZXJydXB0IHR5cGUgaXMgU1BJLCBGYWxsaW5nIGVkZ2UKPiA+ID4gPiA+IHdpbGwgdHJpZ2dlciB0 aGUgaW50ZXJydXB0LiBCdXQgdGhlIHJlcXVlc3RfaXJxKDUwLCBoYW5kbGVyLAo+ID4gPiA+ID4g SVJRX1RZUEVfRURHRV9GQUxMSU5HLCAuLi4pIHdpbGwgcmV0dXJuIC1FSU5WQUwuCj4gPiA+ID4g Pgo+ID4gPiA+ID4gVGhlIHF1ZXN0aW9uIGlzLCB3aHkgbXVzdCB0aGUgU1BJIGludGVycnVwdCB1 c2UgSVJRX1RZUEVfRURHRV9SSVNJTkcKPiA+ID4gPiA+IGluc3RlYWQgb2YgSVJRX1RZUEVfRURH RV9GQUxMSU5HPwo+ID4gPiA+Cj4gPiA+ID4gQmVjYXVzZSB0aGF0J3Mgd2hhdCB0aGUgR0lDIGFy Y2hpdGVjdHVyZVsxXSBzYXlzLiBGcm9tIHNlY3Rpb24gMS4yLjEKPiA+ID4gPiAiSW50ZXJydXB0 IFR5cGVzIjoKPiA+ID4gPgo+ID4gPiA+ICJBbiBpbnRlcnJ1cHQgdGhhdCBpcyBlZGdlLXRyaWdn ZXJlZCBoYXMgdGhlIGZvbGxvd2luZyBwcm9wZXJ0eToKPiA+ID4gPiAgICAgICAgIOKAoiBJdCBp cyBhc3NlcnRlZCBvbiBkZXRlY3Rpb24gb2YgYSByaXNpbmcgZWRnZSBvZiBhbiBpbnRlcnJ1cHQg c2lnbmFsCj4gPiA+Cj4gPiA+IFRoaXMgcmlzaW5nIGVkZ2UgZGV0ZWN0aW9uIGlzIG5vdCB0cnVl LCBpdCdzIGFsc28gYXNzZXJ0ZWQgYnkKPiA+ID4gZmFsbGluZyBlZGdlLCBqdXN0IGxpa2UgdGhl IEdJQ0RfSUNGR1IgcmVnaXN0ZXIgc2F5czogQ2hhbmdpbmcgdGhlCj4gPiA+IGludGVycnVwdCBj b25maWd1cmF0aW9uIGJldHdlZW4gbGV2ZWwtc2Vuc2l0aXZlIGFuZCAqZWRnZS10cmlnZ2VyZWQK PiA+ID4gKGluIGVpdGhlciBkaXJlY3Rpb24pKiBhdCBhIHRpbWUgd2hlbiB0aGVyZSBpcyBhIHBl bmRpbmcgaW50ZXJydXB0Cj4gPiA+IC4uLiwKPiA+Cj4gPiBMZXQgbWUgZmluaXNoIHRoZSBzZW50 ZW5jZSBmb3IgeW91Ogo+ID4KPiA+IDxxdW90ZT4KPiA+IC4uLiB3aWxsIGxlYXZlIHRoZSBpbnRl cnJ1cHQgaW4gYW4gVU5LTk9XTiBwZW5kaW5nIHN0YXRlLgo+ID4gPC9xdW90ZT4KPiAKPiBDb250 ZXh0IHNlbnNpdGl2ZShyZWdpc3Rlci11cGRhdGUgbGVhdmVzIFVOS05PV04gcGVuZGluZykgYW5k Cj4gCj4gPgo+ID4gYW5kIHRoZSBkaXJlY3Rpb24gaGVyZSBpcyBhYm91dCB0aGUgY29uZmlndXJh dGlvbiBiaXQsIG5vdCB0aGUgZWRnZQo+ID4gZGlyZWN0aW9uLgo+IAo+IHdpdGggdGhpcyhjb25m aWd1cmF0aW9uIGJpdDogZWl0aGVyIGxldmVsLXNlbnNpdGl2ZSBvcgo+IGVkZ2UtdHJpZ2dlcmVk KSwgYnV0IGl0IGRvZXNuJ3QgbWF0dGVyLgo+IAo+ID4KPiA+ID4gd2hpY2ggaGFzIGJlZW4gY29u ZmlybWVkIGJ5IEdJQy01MDAgb24gbXkgcGxhdGZvcm0uCj4gPgo+ID4gRnJvbSB0aGUgR0lDNTAw IHIxcDEgVFJNLCBwYWdlIDItODoKPiA+Cj4gPiA8cXVvdGU+Cj4gPiBTUElzIGFyZSBnZW5lcmF0 ZWQgZWl0aGVyIGJ5IHdpcmUgaW5wdXRzIG9yIGJ5IHdyaXRlcyB0byB0aGUgQVhJNAo+ID4gc2xh dmUgcHJvZ3JhbW1pbmcgaW50ZXJmYWNlLiAgVGhlIEdJQy01MDAgY2FuIHN1cHBvcnQgdXAgdG8g OTYwIFNQSXMKPiA+IGNvcnJlc3BvbmRpbmcgdG8gdGhlIGV4dGVybmFsIHNwaVs5OTE6MzJdIHNp Z25hbC4gVGhlIG51bWJlciBvZiBTUElzCj4gPiBhdmFpbGFibGUgZGVwZW5kcyBvbiB0aGUgaW1w bGVtZW50ZWQgY29uZmlndXJhdGlvbi4gVGhlIHBlcm1pdHRlZAo+ID4gdmFsdWVzIGFyZSAzMi05 NjAsIGluIHN0ZXBzIG9mIDMyLiBUaGUgZmlyc3QgU1BJIGhhcyBhbiBJRCBudW1iZXIgb2YKPiA+ IDMyLiBZb3UgY2FuIGNvbmZpZ3VyZSB3aGV0aGVyIGVhY2ggU1BJIGlzIHRyaWdnZXJlZCBvbiBh IHJpc2luZyBlZGdlCj4gPiBvciBpcyBhY3RpdmUtSElHSCBsZXZlbC1zZW5zaXRpdmUuCj4gPiA8 L3F1b3RlPgo+ID4KPiA+IFNvIEkgaGF2ZSBubyBpZGVhIHdoYXQgeW91IGFyZSB0YWxraW5nIGFi b3V0LCBidXQgeW91IGRlZmluaXRlbHkgaGF2ZQo+ID4gdGhlIHdyb25nIGVuZCBvZiB0aGUgc3Rp Y2suIEJvdGggdGhlIGFyY2hpdGVjdHVyZSBhbmQgdGhlCj4gPiBpbXBsZW1lbnRhdGlvbnMgYXJl IGFsaWduZWQgd2l0aCB3aGF0IHRoZSBHSUMgZHJpdmVycyBkby4KPiAKPiBXaGF0IEkgYW0gdGFs a2luZyBhYm91dCBpcyAtIFRoZSBTUEkgaXMgdHJpZ2dlcmVkIG9uIGEgcmlzaW5nIGVkZ2UKPiBv bmx5LCB3aGlsZSB0aGUgZmFsbGluZyBlZGdlIGlzIG5vdCBhcyB0aGUgZG9jdW1lbnQgc2F5cy4g QnV0IEkndmUKPiBvYnNlcnZlZCB0aGUgZmFsbGluZyBlZGdlIGRvZXMgdHJpZ2dlciB0aGUgU1BJ IGludGVycnVwdCBvbiBteQo+IHBsYXRmb3JtICh0aGUgU09DIGlzIE5YUCBTMzJHMjc0QSwgYW4g ZXh0ZXJuYWwgd2FrZXVwIHNpZ25hbCB3aXRoIGhpZ2gKPiB0byBsb3cgdHJhbnNpdGlvbiB0byB3 YWtlIHVwIHRoZSBTT0MgLSAnV2FrZXVwL0ludGVycnVwdCBSaXNpbmctRWRnZQo+IEV2ZW50IEVu YWJsZSBSZWdpc3RlciAoV0lSRUVSKScgYW5kICdXYWtldXAvSW50ZXJydXB0IEZhbGxpbmctRWRn ZQo+IEV2ZW50IEVuYWJsZSBSZWdpc3RlciAoV0lGRUVSKScsIFdJRkVFUiBzZXQgMSBhbmQgV0lS RUVSICBzZXQgMAo+IHdvcmtzKS4KClRoaXMgaXMgdGh1cyBkcml2ZW4gYnkgYW4gZXh0ZXJuYWwg cGllY2Ugb2YgSFcsIHdoaWNoLCBJIGV4cGVjdCwgd291bGQKcGVyZm9ybSB0aGUgc2lnbmFsIGNv bnZlcnNpb24uCgo+IAo+IEkgZG9uJ3Qga25vdyB3aHkgdGhlIEdJQyBoYXMgc3VjaCBhIGJlaGF2 aW9yIGFuZCB3aGF0IHRoZSBzdWJ0bGUKPiByYXRpb25hbGUgaXMgYmVoaW5kIHRoaXMsIHNvIGp1 c3QgbWFyayB0aGlzIGFzIGEgcmVjb3JkLi4uCgpJZiB5b3UgY2FuIHByb3ZlIHRoYXQgdGhlIEdJ QyBpdHNlbGYgKGFuZCBub3Qgc29tZSBwaWVjZSBvZiBIVyBvbiB0aGUKc2lnbmFsIHBhdGgpIGxh dGNoZXMgb24gYSBmYWxsaW5nIGVkZ2UsIHRoZW4gdGhhdCB3b3VsZCBiZSBhIGh1Z2UKYnVnLiBJ IHdvdWxkIGVuY291cmFnZSB5b3UgKG9yIE5YUCkgdG8gcmVwb3J0IGl0IHRvIEFSTSBzbyB0aGF0 IGl0CndvdWxkIGJlIGZpeGVkLgoKTm93LCBnaXZlbiB0aGF0IEdJQzUwMCBoYXMgYmVlbiB3aXRo IHVzIGZvciBvdmVyIDggeWVhcnMsIHN1Y2ggYSBidWcKd291bGQgaGF2ZSBiZWVuIHdpdG5lc3Nl ZCBvbiB0b25zIG9mIGV4aXN0aW5nIHN5c3RlbXMgKGFsbCB0aGUKU1BJLWJhc2VkIE1TSXMgd291 bGQgdHJpZ2dlciB0d2ljZSwgZm9yIGV4YW1wbGUpLiBTaW5jZSB0aGVyZSBoYXMgYmVlbgoodG8g bXkga25vd2xlZGdlKSBubyByZXBvcnQgb2Ygc3VjaCBhbiBpc3N1ZSwgSSBzZXJpb3VzbHkgZG91 YnQgd2hhdAp5b3UgYXJlIHNlZWluZyBpcyBhIEdJQyBtaXNiZWhhdmlvdXIuCgoJTS4KCi0tIApX aXRob3V0IGRldmlhdGlvbiBmcm9tIHRoZSBub3JtLCBwcm9ncmVzcyBpcyBub3QgcG9zc2libGUu CgpfX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fXwpsaW51eC1h cm0ta2VybmVsIG1haWxpbmcgbGlzdApsaW51eC1hcm0ta2VybmVsQGxpc3RzLmluZnJhZGVhZC5v cmcKaHR0cDovL2xpc3RzLmluZnJhZGVhZC5vcmcvbWFpbG1hbi9saXN0aW5mby9saW51eC1hcm0t a2VybmVsCg== From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 87F54C433EF for ; Thu, 26 May 2022 12:52:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1344573AbiEZMww (ORCPT ); Thu, 26 May 2022 08:52:52 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40598 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235381AbiEZMwt (ORCPT ); Thu, 26 May 2022 08:52:49 -0400 Received: from ams.source.kernel.org (ams.source.kernel.org [145.40.68.75]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 06B902ED46 for ; Thu, 26 May 2022 05:52:47 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id 6BB46B82058 for ; Thu, 26 May 2022 12:52:46 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id E6244C385A9; Thu, 26 May 2022 12:52:44 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1653569564; bh=Z3C6dkYdPm8lWq2xILiBEXeVjfcYz6sTr481QH2GFp4=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=YdFlNA8n+XGTjQ7ypalb4t9BC9Ib5TAVbONZ1gNnJ6QPJ51RnQw8NYxoRbM4P0sY6 Hiq5RTMPDLMRMWBht8+FYLqcl13WNd7eriPi/WK+O1CFtrgWv8KPUAeCl7J57aTLcx zLhjZqcZD5z954/dlKPhE0YKV+xi2H1Lfv4nTPZ2RbIOBFfRRnWTQq8b8aDdKQzvP2 73gR3/f5bsH3sGYVo+jKBUSUR5zC7FOnWfCEY6PHysCBZccqqELZBkdGUoBKXXu3pK Q4vNvS3MfESk3f7723cgVJ4lEr4XEBHQCyAwnCH79X5u2rs+3eR61ZtVf1TrTcD844 9dF8AtOxNq2WQ== Received: from athedsl-4557779.home.otenet.gr ([94.70.87.219] helo=wait-a-minute.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1nuCyo-00Dquf-Cp; Thu, 26 May 2022 13:52:42 +0100 Date: Thu, 26 May 2022 13:52:40 +0100 Message-ID: <87czg0mp5z.wl-maz@kernel.org> From: Marc Zyngier To: richard clark Cc: Robin Murphy , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, s32@nxp.com, leoyang.li@nxp.com, catalin-dan.udma@nxp.com, bogdan.hamciuc@nxp.com, bogdan.folea@nxp.com, ciprianmarian.costea@nxp.com, radu-nicolae.pirea@nxp.com, ghennadi.procopciuc@nxp.com Subject: Re: Question about SPIs' interrupt trigger type restrictions In-Reply-To: References: <35f95ba3-8a7b-7918-0f9d-e14274a5ffe9@arm.com> <87ee0gn5rq.wl-maz@kernel.org> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/27.1 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-SA-Exim-Connect-IP: 94.70.87.219 X-SA-Exim-Rcpt-To: richard.xnu.clark@gmail.com, robin.murphy@arm.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, s32@nxp.com, leoyang.li@nxp.com, catalin-dan.udma@nxp.com, bogdan.hamciuc@nxp.com, bogdan.folea@nxp.com, ciprianmarian.costea@nxp.com, radu-nicolae.pirea@nxp.com, ghennadi.procopciuc@nxp.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, 26 May 2022 13:09:32 +0100, richard clark wrote: >=20 > CC'ing some nxp guys for the S32G274A SOC... >=20 > On Thu, May 26, 2022 at 2:54 PM Marc Zyngier wrote: > > > > On Thu, 26 May 2022 04:44:41 +0100, > > richard clark wrote: > > > > > > On Thu, May 26, 2022 at 3:14 AM Robin Murphy w= rote: > > > > > > > > On 2022-05-25 11:01, richard clark wrote: > > > > > Hi Marc, > > > > > > > > > > For below code snippet about SPI interrupt trigger type: > > > > > > > > > > static int gic_set_type(struct irq_data *d, unsigned int type) > > > > > { > > > > > ... > > > > > /* SPIs have restrictions on the supported types */ > > > > > if ((range =3D=3D SPI_RANGE || range =3D=3D ESPI_RANGE) = && > > > > > type !=3D IRQ_TYPE_LEVEL_HIGH && type !=3D IRQ_TYPE_= EDGE_RISING) > > > > > return -EINVAL; > > > > > ... > > > > > } > > > > > > > > > > We have a device at hand whose interrupt type is SPI, Falling edge > > > > > will trigger the interrupt. But the request_irq(50, handler, > > > > > IRQ_TYPE_EDGE_FALLING, ...) will return -EINVAL. > > > > > > > > > > The question is, why must the SPI interrupt use IRQ_TYPE_EDGE_RIS= ING > > > > > instead of IRQ_TYPE_EDGE_FALLING? > > > > > > > > Because that's what the GIC architecture[1] says. From section 1.2.1 > > > > "Interrupt Types": > > > > > > > > "An interrupt that is edge-triggered has the following property: > > > > =E2=80=A2 It is asserted on detection of a rising edge of a= n interrupt signal > > > > > > This rising edge detection is not true, it's also asserted by > > > falling edge, just like the GICD_ICFGR register says: Changing the > > > interrupt configuration between level-sensitive and *edge-triggered > > > (in either direction)* at a time when there is a pending interrupt > > > ..., > > > > Let me finish the sentence for you: > > > > > > ... will leave the interrupt in an UNKNOWN pending state. > > >=20 > Context sensitive(register-update leaves UNKNOWN pending) and >=20 > > > > and the direction here is about the configuration bit, not the edge > > direction. >=20 > with this(configuration bit: either level-sensitive or > edge-triggered), but it doesn't matter. >=20 > > > > > which has been confirmed by GIC-500 on my platform. > > > > From the GIC500 r1p1 TRM, page 2-8: > > > > > > SPIs are generated either by wire inputs or by writes to the AXI4 > > slave programming interface. The GIC-500 can support up to 960 SPIs > > corresponding to the external spi[991:32] signal. The number of SPIs > > available depends on the implemented configuration. The permitted > > values are 32-960, in steps of 32. The first SPI has an ID number of > > 32. You can configure whether each SPI is triggered on a rising edge > > or is active-HIGH level-sensitive. > > > > > > So I have no idea what you are talking about, but you definitely have > > the wrong end of the stick. Both the architecture and the > > implementations are aligned with what the GIC drivers do. >=20 > What I am talking about is - The SPI is triggered on a rising edge > only, while the falling edge is not as the document says. But I've > observed the falling edge does trigger the SPI interrupt on my > platform (the SOC is NXP S32G274A, an external wakeup signal with high > to low transition to wake up the SOC - 'Wakeup/Interrupt Rising-Edge > Event Enable Register (WIREER)' and 'Wakeup/Interrupt Falling-Edge > Event Enable Register (WIFEER)', WIFEER set 1 and WIREER set 0 > works). This is thus driven by an external piece of HW, which, I expect, would perform the signal conversion. >=20 > I don't know why the GIC has such a behavior and what the subtle > rationale is behind this, so just mark this as a record... If you can prove that the GIC itself (and not some piece of HW on the signal path) latches on a falling edge, then that would be a huge bug. I would encourage you (or NXP) to report it to ARM so that it would be fixed. Now, given that GIC500 has been with us for over 8 years, such a bug would have been witnessed on tons of existing systems (all the SPI-based MSIs would trigger twice, for example). Since there has been (to my knowledge) no report of such an issue, I seriously doubt what you are seeing is a GIC misbehaviour. M. --=20 Without deviation from the norm, progress is not possible.