From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id EBBDFC2D0A3 for ; Thu, 29 Oct 2020 08:10:51 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 927BE2071A for ; Thu, 29 Oct 2020 08:10:51 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 927BE2071A Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linux.intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 0C8286E85B; Thu, 29 Oct 2020 08:10:51 +0000 (UTC) Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by gabe.freedesktop.org (Postfix) with ESMTPS id 5FDE36E85B for ; Thu, 29 Oct 2020 08:10:49 +0000 (UTC) IronPort-SDR: LN6b83k9e6PgDS40BwdMkgbhNjKXRFi33w1wSREjDV1brVObf5VGH3IDzoU9m3NCpDtBlmW/jB /ooZajkeuIfg== X-IronPort-AV: E=McAfee;i="6000,8403,9788"; a="164897195" X-IronPort-AV: E=Sophos;i="5.77,429,1596524400"; d="scan'208";a="164897195" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga004.jf.intel.com ([10.7.209.38]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Oct 2020 01:10:45 -0700 IronPort-SDR: 2Fj+aYiA13r/6zJhIgwlHra7FH4hbpNzx/ywe5QvHqVKYY2FqukzzeuwYKOZ+gKOByZasL6029 5wL2i/Tb+l8Q== X-IronPort-AV: E=Sophos;i="5.77,429,1596524400"; d="scan'208";a="469046350" Received: from rsexton-mobl1.ger.corp.intel.com (HELO localhost) ([10.252.5.42]) by orsmga004-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Oct 2020 01:10:41 -0700 From: Jani Nikula To: Lee Shawn C , intel-gfx@lists.freedesktop.org In-Reply-To: <20201028144312.12520-1-shawn.c.lee@intel.com> Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo References: <20201028144312.12520-1-shawn.c.lee@intel.com> Date: Thu, 29 Oct 2020 10:10:39 +0200 Message-ID: <87d011iha8.fsf@intel.com> MIME-Version: 1.0 Subject: Re: [Intel-gfx] [PATCH] drm/i915/rkl: new rkl ddc map for different PCH X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Cooper Chiou Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" On Wed, 28 Oct 2020, Lee Shawn C wrote: > After boot into kernel. Driver configured ddc pin mapping based on > predefined table in parse_ddi_port(). Now driver configure rkl > ddc pin mapping depends on icp_ddc_pin_map[]. Then this table will > give incorrect gmbus port number to cause HDMI can't work. > > Refer to commit d0a89527d06 ("drm/i915/rkl: Add DDC pin mapping"). > Create two ddc pin table for rkl TGP and CMP pch. Then HDMI can > works properly on rkl. > > Cc: Matt Roper > Cc: Aditya Swarup > Cc: Anusha Srivatsa > Cc: Jani Nikula > Cc: Cooper Chiou > Cc: Khaled Almahallawy > Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/2577 > Signed-off-by: Lee Shawn C > --- > drivers/gpu/drm/i915/display/intel_bios.c | 22 ++++++++++++++++++- > drivers/gpu/drm/i915/display/intel_vbt_defs.h | 4 ++++ > 2 files changed, 25 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c > index a0a41ec5c341..f2c4772e4c7f 100644 > --- a/drivers/gpu/drm/i915/display/intel_bios.c > +++ b/drivers/gpu/drm/i915/display/intel_bios.c > @@ -1597,12 +1597,32 @@ static const u8 icp_ddc_pin_map[] = { > [TGL_DDC_BUS_PORT_6] = GMBUS_PIN_14_TC6_TGP, > }; > > +static const u8 rkl_pch_tgp_ddc_pin_map[] = { > + [RKL_DDC_BUS_DDI_B] = GMBUS_PIN_2_BXT, > + [RKL_DDC_BUS_DDI_D] = GMBUS_PIN_9_TC1_ICP, > + [RKL_DDC_BUS_DDI_E] = GMBUS_PIN_10_TC2_ICP, > +}; > + > +static const u8 rkl_pch_cmp_ddc_pin_map[] = { > + [RKL_DDC_BUS_DDI_B] = GMBUS_PIN_2_BXT, > + [RKL_DDC_BUS_DDI_D] = GMBUS_PIN_3_BXT, > + [RKL_DDC_BUS_DDI_E] = GMBUS_PIN_4_CNP, > +}; > + > static u8 map_ddc_pin(struct drm_i915_private *dev_priv, u8 vbt_pin) > { > const u8 *ddc_pin_map; > int n_entries; > > - if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP) { > + if (IS_ROCKETLAKE(dev_priv)) { Why the platform check for a PCH based thing? BR, Jani. > + if (INTEL_PCH_TYPE(dev_priv) >= PCH_TGP) { > + ddc_pin_map = rkl_pch_tgp_ddc_pin_map; > + n_entries = ARRAY_SIZE(rkl_pch_tgp_ddc_pin_map); > + } else { > + ddc_pin_map = rkl_pch_cmp_ddc_pin_map; > + n_entries = ARRAY_SIZE(rkl_pch_cmp_ddc_pin_map); > + } > + } else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP) { > ddc_pin_map = icp_ddc_pin_map; > n_entries = ARRAY_SIZE(icp_ddc_pin_map); > } else if (HAS_PCH_CNP(dev_priv)) { > diff --git a/drivers/gpu/drm/i915/display/intel_vbt_defs.h b/drivers/gpu/drm/i915/display/intel_vbt_defs.h > index 6faabd4f6d49..3418c00446c1 100644 > --- a/drivers/gpu/drm/i915/display/intel_vbt_defs.h > +++ b/drivers/gpu/drm/i915/display/intel_vbt_defs.h > @@ -315,6 +315,10 @@ enum vbt_gmbus_ddi { > ICL_DDC_BUS_DDI_A = 0x1, > ICL_DDC_BUS_DDI_B, > TGL_DDC_BUS_DDI_C, > + RKL_DDC_BUS_DDI_B = 0x1, > + RKL_DDC_BUS_DDI_C, > + RKL_DDC_BUS_DDI_D, > + RKL_DDC_BUS_DDI_E, > ICL_DDC_BUS_PORT_1 = 0x4, > ICL_DDC_BUS_PORT_2, > ICL_DDC_BUS_PORT_3, -- Jani Nikula, Intel Open Source Graphics Center _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx