Re: [Intel-gfx] [PATCH 3/3] drm/i915/gt: Stop invalidating the PD cachelines for gen7

[Mika Kuoppala <mika.kuoppala@linux.intel.com>]

Chris Wilson <chris@chris-wilson.co.uk> writes:

> Trust that the HW does the right thing after simply updating the
> PD_DIR_BASE?

Bspec offers an invalidate before writing the base.

So, lets assume the DCLV write is superfluous as it will be
the same.

Then the sequence would be TLB_INVLIDATE followed by
PP_DIR_BASE (which will all pds)

-Mika

>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/gt/intel_ring_submission.c | 10 +---------
>  1 file changed, 1 insertion(+), 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_ring_submission.c b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
> index f915a63e1110..23f4fc2669d1 100644
> --- a/drivers/gpu/drm/i915/gt/intel_ring_submission.c
> +++ b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
> @@ -1341,14 +1341,10 @@ static int load_pd_dir(struct i915_request *rq,
>  	const struct intel_engine_cs * const engine = rq->engine;
>  	u32 *cs;
>  
> -	cs = intel_ring_begin(rq, 12);
> +	cs = intel_ring_begin(rq, 6);
>  	if (IS_ERR(cs))
>  		return PTR_ERR(cs);
>  
> -	*cs++ = MI_LOAD_REGISTER_IMM(1);
> -	*cs++ = i915_mmio_reg_offset(RING_PP_DIR_DCLV(engine->mmio_base));
> -	*cs++ = valid;
> -
>  	*cs++ = MI_LOAD_REGISTER_IMM(1);
>  	*cs++ = i915_mmio_reg_offset(RING_PP_DIR_BASE(engine->mmio_base));
>  	*cs++ = px_base(ppgtt->pd)->ggtt_offset << 10;
> @@ -1359,10 +1355,6 @@ static int load_pd_dir(struct i915_request *rq,
>  	*cs++ = intel_gt_scratch_offset(engine->gt,
>  					INTEL_GT_SCRATCH_FIELD_DEFAULT);
>  
> -	*cs++ = MI_LOAD_REGISTER_IMM(1);
> -	*cs++ = i915_mmio_reg_offset(RING_INSTPM(engine->mmio_base));
> -	*cs++ = _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE);
> -
>  	intel_ring_advance(rq, cs);
>  
>  	return rq->engine->emit_flush(rq, EMIT_FLUSH);
> -- 
> 2.25.0
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