From: "Alex Bennée" <alex.bennee@linaro.org>
To: "Emilio G. Cota" <cota@braap.org>
Cc: qemu-devel@nongnu.org, Paolo Bonzini <pbonzini@redhat.com>,
Peter Crosthwaite <crosthwaite.peter@gmail.com>,
Richard Henderson <rth@twiddle.net>,
Eduardo Habkost <ehabkost@redhat.com>
Subject: Re: [Qemu-devel] [PATCH 5/6] target/i386/translate: use thread-local storage in !user-mode
Date: Mon, 10 Sep 2018 10:17:53 +0100 [thread overview]
Message-ID: <87d0tld83i.fsf@linaro.org> (raw)
In-Reply-To: <20180903171831.15446-6-cota@braap.org>
Emilio G. Cota <cota@braap.org> writes:
> Needed for MTTCG.
>
> Signed-off-by: Emilio G. Cota <cota@braap.org>
> ---
> target/i386/translate.c | 24 ++++++++++++++++--------
> 1 file changed, 16 insertions(+), 8 deletions(-)
>
> diff --git a/target/i386/translate.c b/target/i386/translate.c
> index 1f9d1d9b24..9a6a72e205 100644
> --- a/target/i386/translate.c
> +++ b/target/i386/translate.c
> @@ -71,26 +71,34 @@
>
> //#define MACRO_TEST 1
>
> +/* we need thread-local storage for mttcg */
> +#ifdef CONFIG_USER_ONLY
> +#define I386_THREAD
> +#else
> +#define I386_THREAD __thread
> +#endif
> +
I'm confused - as we can have multi-threaded user space don't the same
requirements apply?
> /* global register indexes */
> -static TCGv cpu_A0;
> -static TCGv cpu_cc_dst, cpu_cc_src, cpu_cc_src2, cpu_cc_srcT;
> +static TCGv cpu_cc_dst, cpu_cc_src, cpu_cc_src2;
> static TCGv_i32 cpu_cc_op;
> static TCGv cpu_regs[CPU_NB_REGS];
> static TCGv cpu_seg_base[6];
> static TCGv_i64 cpu_bndl[4];
> static TCGv_i64 cpu_bndu[4];
> /* local temps */
> -static TCGv cpu_T0, cpu_T1;
> +static I386_THREAD TCGv cpu_cc_srcT;
> +static I386_THREAD TCGv cpu_A0;
> +static I386_THREAD TCGv cpu_T0, cpu_T1;
> /* local register indexes (only used inside old micro ops) */
> -static TCGv cpu_tmp0, cpu_tmp4;
> -static TCGv_ptr cpu_ptr0, cpu_ptr1;
> -static TCGv_i32 cpu_tmp2_i32, cpu_tmp3_i32;
> -static TCGv_i64 cpu_tmp1_i64;
> +static I386_THREAD TCGv cpu_tmp0, cpu_tmp4;
> +static I386_THREAD TCGv_ptr cpu_ptr0, cpu_ptr1;
> +static I386_THREAD TCGv_i32 cpu_tmp2_i32, cpu_tmp3_i32;
> +static I386_THREAD TCGv_i64 cpu_tmp1_i64;
>
> #include "exec/gen-icount.h"
>
> #ifdef TARGET_X86_64
> -static int x86_64_hregs;
> +static I386_THREAD int x86_64_hregs;
> #endif
>
> typedef struct DisasContext {
--
Alex Bennée
next prev parent reply other threads:[~2018-09-10 9:18 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-09-03 17:18 [Qemu-devel] [PATCH 0/6] i386 + x86_64 mttcg Emilio G. Cota
2018-09-03 17:18 ` [Qemu-devel] [PATCH 1/6] qsp: drop atomics when using the seqlock Emilio G. Cota
2018-09-09 23:32 ` Paolo Bonzini
2018-09-10 15:44 ` Emilio G. Cota
2018-09-11 11:11 ` Paolo Bonzini
2018-09-03 17:18 ` [Qemu-devel] [PATCH 2/6] test-rcu-list: avoid torn accesses to n_reclaims and n_nodes_removed Emilio G. Cota
2018-09-04 17:37 ` Murilo Opsfelder Araujo
2018-09-04 19:35 ` Emilio G. Cota
2018-09-04 20:56 ` Murilo Opsfelder Araujo
2018-09-04 21:32 ` Emilio G. Cota
2018-09-11 11:25 ` Paolo Bonzini
2018-09-03 17:18 ` [Qemu-devel] [PATCH 3/6] atomic: fix comment s/x64_64/x86_64/ Emilio G. Cota
2018-09-10 9:12 ` Alex Bennée
2018-09-03 17:18 ` [Qemu-devel] [PATCH 4/6] cpus: initialize timers_state.vm_clock_lock Emilio G. Cota
2018-09-10 9:13 ` Alex Bennée
2018-09-03 17:18 ` [Qemu-devel] [PATCH 5/6] target/i386/translate: use thread-local storage in !user-mode Emilio G. Cota
2018-09-10 9:17 ` Alex Bennée [this message]
2018-09-10 12:30 ` Emilio G. Cota
2018-09-10 13:43 ` Alex Bennée
2018-09-11 11:24 ` Paolo Bonzini
2018-09-11 17:21 ` Emilio G. Cota
2018-09-03 17:18 ` [Qemu-devel] [PATCH 6/6] configure: enable mttcg for i386 and x86_64 Emilio G. Cota
2018-09-11 11:25 ` [Qemu-devel] [PATCH 0/6] i386 + x86_64 mttcg Paolo Bonzini
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