Re: [GLK MIPI DSI V6 0/7] GLK MIPI DSI VIDEO MODE PATCHES

[Jani Nikula <jani.nikula@intel.com>]

On Fri, 17 Feb 2017, Madhav Chauhan <madhav.chauhan@intel.com> wrote:
> The patches in this list enable MIPI DSI video mode
> support for GLK platform. Tesed locally.
> v2: Renamed bitfields macros as per review comments(Jani)
> v3: Code alignment/abstraction as per arch (Jani review comments)
> v4: Fix MIPI DSI disable sequence. Review comments(Jani)
> v5: Review comments addressed for restructuring code (Jani & Ander)
> v6: Changes in enable i/o sequence, remove compile warning (Jani review comments)
>

I've pushed everything here to drm-intel-next-queued except patch 3/7
("drm/i915/glk: Add MIPIIO Enable/disable sequence"), which would
conflict with Hans' patches [1] that I'm about to push next.

Thanks for the patches.

BR,
Jani.

[1] http://mid.mail-archive.com/cover.1488273823.git.jani.nikula@intel.com


> Deepak M (6):
>   drm/i915/glk: Program dphy param reg for GLK
>   drm/i915/glk: Program new MIPI DSI PHY registers for GLK
>   drm/i915/glk: Add MIPIIO Enable/disable sequence
>   drm/i915/glk: Add DSI PLL divider range for glk
>   drm/i915i/glk: Program MIPI_CLOCK_CTRL only for BXT
>   drm/i915/glk: Program txesc clock divider for GLK
>
> Madhav Chauhan (1):
>   drm/i915/glk: Validate only DSI PORT A PLL divider
>
>  drivers/gpu/drm/i915/i915_reg.h            |  17 +++
>  drivers/gpu/drm/i915/intel_dsi.c           | 214 +++++++++++++++++++++++++++--
>  drivers/gpu/drm/i915/intel_dsi_panel_vbt.c |  31 +++--
>  drivers/gpu/drm/i915/intel_dsi_pll.c       | 129 +++++++++++++----
>  4 files changed, 340 insertions(+), 51 deletions(-)

-- 
Jani Nikula, Intel Open Source Technology Center
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