Re: [PATCH v2] drm/i915/chv: Remove DPIO force latency causing interpair skew issue

From: Jani Nikula <jani.nikula@linux.intel.com>
To: "Ville Syrjälä" <ville.syrjala@linux.intel.com>,
	clinton.a.taylor@intel.com
Cc: Intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH v2] drm/i915/chv: Remove DPIO force latency causing interpair skew issue
Date: Fri, 10 Apr 2015 14:34:27 +0300	[thread overview]
Message-ID: <87d23cqksc.fsf@intel.com> (raw)
In-Reply-To: <20150410105410.GW17410@intel.com>

On Fri, 10 Apr 2015, Ville Syrjälä <ville.syrjala@linux.intel.com> wrote:
> On Thu, Apr 09, 2015 at 01:42:06PM -0700, clinton.a.taylor@intel.com wrote:
>> From: Clint Taylor <clinton.a.taylor@intel.com>
>> 
>> Latest version of the "CHV DPIO programming notes" no longer requires writes
>> to TX DW 11 to fix a +2UI interpair skew issue. The current code from
>> April 2014 was actually causing additional skew issues between all
>> TMDS pairs.
>> 
>> ver2: added same treatment to intel_dp.c based on Ville's testing.
>> 
>> Cc: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= <ville.syrjala@linux.intel.com>
>> Signed-off-by: Clint Taylor <clinton.a.taylor@intel.com>
>
> Yep this fixes the DP link training issues on both of the problematic
> displays I have (HP ZR24w and ASUS PB278Q). Nice work.
>
> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Tested-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Pushed to drm-intel-next-fixes (because chv support is no longer flagged
preliminary since drm-next and v4.1). Thanks for the patch and review.

BR,
Jani.

>
>> ---
>>  drivers/gpu/drm/i915/intel_dp.c   |    5 -----
>>  drivers/gpu/drm/i915/intel_hdmi.c |    5 -----
>>  2 files changed, 10 deletions(-)
>> 
>> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
>> index 1b87969..f106763 100644
>> --- a/drivers/gpu/drm/i915/intel_dp.c
>> +++ b/drivers/gpu/drm/i915/intel_dp.c
>> @@ -2740,11 +2740,6 @@ static void chv_pre_enable_dp(struct intel_encoder *encoder)
>>  
>>  	/* Program Tx lane latency optimal setting*/
>>  	for (i = 0; i < 4; i++) {
>> -		/* Set the latency optimal bit */
>> -		data = (i == 1) ? 0x0 : 0x6;
>> -		vlv_dpio_write(dev_priv, pipe, CHV_TX_DW11(ch, i),
>> -				data << DPIO_FRC_LATENCY_SHFIT);
>> -
>>  		/* Set the upar bit */
>>  		data = (i == 1) ? 0x0 : 0x1;
>>  		vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i),
>> diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
>> index 26222e6..3cef326 100644
>> --- a/drivers/gpu/drm/i915/intel_hdmi.c
>> +++ b/drivers/gpu/drm/i915/intel_hdmi.c
>> @@ -1515,11 +1515,6 @@ static void chv_hdmi_pre_enable(struct intel_encoder *encoder)
>>  
>>  	/* Program Tx latency optimal setting */
>>  	for (i = 0; i < 4; i++) {
>> -		/* Set the latency optimal bit */
>> -		data = (i == 1) ? 0x0 : 0x6;
>> -		vlv_dpio_write(dev_priv, pipe, CHV_TX_DW11(ch, i),
>> -				data << DPIO_FRC_LATENCY_SHFIT);
>> -
>>  		/* Set the upar bit */
>>  		data = (i == 1) ? 0x0 : 0x1;
>>  		vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i),
>> -- 
>> 1.7.9.5
>
> -- 
> Ville Syrjälä
> Intel OTC
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Jani Nikula, Intel Open Source Technology Center
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