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From: Jani Nikula <jani.nikula@linux.intel.com>
To: Antti Koskipaa <antti.koskipaa@linux.intel.com>,
	intel-gfx@lists.freedesktop.org
Subject: Re: [RFC v2] drm/i915: Clean up display pipe register accesses
Date: Wed, 04 Dec 2013 17:24:24 +0200	[thread overview]
Message-ID: <87d2lcwsev.fsf@intel.com> (raw)
In-Reply-To: <1385559934-27523-1-git-send-email-antti.koskipaa@linux.intel.com>

On Wed, 27 Nov 2013, Antti Koskipaa <antti.koskipaa@linux.intel.com> wrote:
> v2: Reorganize array indexing so that full offsets can be used as
> is. It makes grepping for registers in i915_reg.h much easier. Also
> move offset arrays to intel_device_info.

Overall, I like this approach better than v1. Comments follow.

> Upcoming hardware will not have the various display pipe register
> ranges evenly spaced in memory. Change register address calculations
> into array lookups.
>
> Tested on SandyBridge and VLV/BYT.
>
> I left the UMS cruft untouched.
>
> Signed-off-by: Antti Koskipaa <antti.koskipaa@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/i915_drv.c | 56 +++++++++++++++++++++++
>  drivers/gpu/drm/i915/i915_drv.h |  9 +++-
>  drivers/gpu/drm/i915/i915_reg.h | 99 ++++++++++++++++++++++++++---------------
>  3 files changed, 127 insertions(+), 37 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index 24d58b0..95e17a2 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -161,16 +161,48 @@ extern int intel_agp_enabled;
>  static int intel_agp_enabled;
>  #endif
>  
> +#define GEN_DEFAULT_PIPEOFFSETS \
> +	.pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET }, \
> +	.trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \
> +			   TRANSCODER_C_OFFSET, TRANSCODER_EDP_OFFSET }, \
> +	.dpll_offsets = { DPLL_A_OFFSET, DPLL_B_OFFSET }, \
> +	.dpll_md_offsets = { DPLL_A_MD_OFFSET, DPLL_B_MD_OFFSET }, \
> +	.palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET },
> +
> +#define GEN7_PIPEOFFSETS \
> +	.pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, PIPE_C_OFFSET }, \
> +	.trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \
> +			   TRANSCODER_C_OFFSET, TRANSCODER_EDP_OFFSET }, \
> +	.dpll_offsets = { DPLL_A_OFFSET, DPLL_B_OFFSET }, \
> +	.dpll_md_offsets = { DPLL_A_MD_OFFSET, DPLL_B_MD_OFFSET }, \
> +	.palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET },
> +
> +#define VLV_PIPEOFFSETS \
> +	.pipe_offsets = { PIPE_A_OFFSET+VLV_DISPLAY_BASE, \
> +			  PIPE_B_OFFSET+VLV_DISPLAY_BASE }, \
> +	.trans_offsets = { TRANSCODER_A_OFFSET+VLV_DISPLAY_BASE, \
> +			   TRANSCODER_B_OFFSET+VLV_DISPLAY_BASE, \
> +			   TRANSCODER_C_OFFSET+VLV_DISPLAY_BASE, \
> +			   TRANSCODER_EDP_OFFSET+VLV_DISPLAY_BASE }, \
> +	.dpll_offsets = { DPLL_A_OFFSET+VLV_DISPLAY_BASE, \
> +			  DPLL_B_OFFSET+VLV_DISPLAY_BASE }, \
> +	.dpll_md_offsets = { DPLL_A_MD_OFFSET+VLV_DISPLAY_BASE, \
> +			     DPLL_B_MD_OFFSET+VLV_DISPLAY_BASE }, \
> +	.palette_offsets = { PALETTE_A_OFFSET+VLV_DISPLAY_BASE, \
> +			     PALETTE_B_OFFSET+VLV_DISPLAY_BASE },

Please drop the last comma in the defines above...

> +
>  static const struct intel_device_info intel_i830_info = {
>  	.gen = 2, .is_mobile = 1, .cursor_needs_physical = 1, .num_pipes = 2,
>  	.has_overlay = 1, .overlay_needs_physical = 1,
>  	.ring_mask = RENDER_RING,
> +	GEN_DEFAULT_PIPEOFFSETS

...and add it here instead so the initialization looks consistent. See
GEN7_FEATURES.

>  };
>  
>  static const struct intel_device_info intel_845g_info = {
>  	.gen = 2, .num_pipes = 1,
>  	.has_overlay = 1, .overlay_needs_physical = 1,
>  	.ring_mask = RENDER_RING,
> +	GEN_DEFAULT_PIPEOFFSETS
>  };
>  
>  static const struct intel_device_info intel_i85x_info = {
> @@ -178,18 +210,21 @@ static const struct intel_device_info intel_i85x_info = {
>  	.cursor_needs_physical = 1,
>  	.has_overlay = 1, .overlay_needs_physical = 1,
>  	.ring_mask = RENDER_RING,
> +	GEN_DEFAULT_PIPEOFFSETS
>  };
>  
>  static const struct intel_device_info intel_i865g_info = {
>  	.gen = 2, .num_pipes = 1,
>  	.has_overlay = 1, .overlay_needs_physical = 1,
>  	.ring_mask = RENDER_RING,
> +	GEN_DEFAULT_PIPEOFFSETS
>  };
>  
>  static const struct intel_device_info intel_i915g_info = {
>  	.gen = 3, .is_i915g = 1, .cursor_needs_physical = 1, .num_pipes = 2,
>  	.has_overlay = 1, .overlay_needs_physical = 1,
>  	.ring_mask = RENDER_RING,
> +	GEN_DEFAULT_PIPEOFFSETS
>  };
>  static const struct intel_device_info intel_i915gm_info = {
>  	.gen = 3, .is_mobile = 1, .num_pipes = 2,
> @@ -197,11 +232,13 @@ static const struct intel_device_info intel_i915gm_info = {
>  	.has_overlay = 1, .overlay_needs_physical = 1,
>  	.supports_tv = 1,
>  	.ring_mask = RENDER_RING,
> +	GEN_DEFAULT_PIPEOFFSETS
>  };
>  static const struct intel_device_info intel_i945g_info = {
>  	.gen = 3, .has_hotplug = 1, .cursor_needs_physical = 1, .num_pipes = 2,
>  	.has_overlay = 1, .overlay_needs_physical = 1,
>  	.ring_mask = RENDER_RING,
> +	GEN_DEFAULT_PIPEOFFSETS
>  };
>  static const struct intel_device_info intel_i945gm_info = {
>  	.gen = 3, .is_i945gm = 1, .is_mobile = 1, .num_pipes = 2,
> @@ -209,6 +246,7 @@ static const struct intel_device_info intel_i945gm_info = {
>  	.has_overlay = 1, .overlay_needs_physical = 1,
>  	.supports_tv = 1,
>  	.ring_mask = RENDER_RING,
> +	GEN_DEFAULT_PIPEOFFSETS
>  };
>  
>  static const struct intel_device_info intel_i965g_info = {
> @@ -216,6 +254,7 @@ static const struct intel_device_info intel_i965g_info = {
>  	.has_hotplug = 1,
>  	.has_overlay = 1,
>  	.ring_mask = RENDER_RING,
> +	GEN_DEFAULT_PIPEOFFSETS
>  };
>  
>  static const struct intel_device_info intel_i965gm_info = {
> @@ -224,6 +263,7 @@ static const struct intel_device_info intel_i965gm_info = {
>  	.has_overlay = 1,
>  	.supports_tv = 1,
>  	.ring_mask = RENDER_RING,
> +	GEN_DEFAULT_PIPEOFFSETS
>  };
>  
>  static const struct intel_device_info intel_g33_info = {
> @@ -231,12 +271,14 @@ static const struct intel_device_info intel_g33_info = {
>  	.need_gfx_hws = 1, .has_hotplug = 1,
>  	.has_overlay = 1,
>  	.ring_mask = RENDER_RING,
> +	GEN_DEFAULT_PIPEOFFSETS
>  };
>  
>  static const struct intel_device_info intel_g45_info = {
>  	.gen = 4, .is_g4x = 1, .need_gfx_hws = 1, .num_pipes = 2,
>  	.has_pipe_cxsr = 1, .has_hotplug = 1,
>  	.ring_mask = RENDER_RING | BSD_RING,
> +	GEN_DEFAULT_PIPEOFFSETS
>  };
>  
>  static const struct intel_device_info intel_gm45_info = {
> @@ -245,18 +287,21 @@ static const struct intel_device_info intel_gm45_info = {
>  	.has_pipe_cxsr = 1, .has_hotplug = 1,
>  	.supports_tv = 1,
>  	.ring_mask = RENDER_RING | BSD_RING,
> +	GEN_DEFAULT_PIPEOFFSETS
>  };
>  
>  static const struct intel_device_info intel_pineview_info = {
>  	.gen = 3, .is_g33 = 1, .is_pineview = 1, .is_mobile = 1, .num_pipes = 2,
>  	.need_gfx_hws = 1, .has_hotplug = 1,
>  	.has_overlay = 1,
> +	GEN_DEFAULT_PIPEOFFSETS
>  };
>  
>  static const struct intel_device_info intel_ironlake_d_info = {
>  	.gen = 5, .num_pipes = 2,
>  	.need_gfx_hws = 1, .has_hotplug = 1,
>  	.ring_mask = RENDER_RING | BSD_RING,
> +	GEN_DEFAULT_PIPEOFFSETS
>  };
>  
>  static const struct intel_device_info intel_ironlake_m_info = {
> @@ -264,6 +309,7 @@ static const struct intel_device_info intel_ironlake_m_info = {
>  	.need_gfx_hws = 1, .has_hotplug = 1,
>  	.has_fbc = 1,
>  	.ring_mask = RENDER_RING | BSD_RING,
> +	GEN_DEFAULT_PIPEOFFSETS
>  };
>  
>  static const struct intel_device_info intel_sandybridge_d_info = {
> @@ -271,6 +317,7 @@ static const struct intel_device_info intel_sandybridge_d_info = {
>  	.need_gfx_hws = 1, .has_hotplug = 1,
>  	.ring_mask = RENDER_RING | BSD_RING | BLT_RING,
>  	.has_llc = 1,
> +	GEN_DEFAULT_PIPEOFFSETS
>  };
>  
>  static const struct intel_device_info intel_sandybridge_m_info = {
> @@ -279,6 +326,7 @@ static const struct intel_device_info intel_sandybridge_m_info = {
>  	.has_fbc = 1,
>  	.ring_mask = RENDER_RING | BSD_RING | BLT_RING,
>  	.has_llc = 1,
> +	GEN_DEFAULT_PIPEOFFSETS
>  };
>  
>  #define GEN7_FEATURES  \
> @@ -290,6 +338,7 @@ static const struct intel_device_info intel_sandybridge_m_info = {
>  static const struct intel_device_info intel_ivybridge_d_info = {
>  	GEN7_FEATURES,
>  	.is_ivybridge = 1,
> +	GEN7_PIPEOFFSETS
>  };
>  
>  static const struct intel_device_info intel_ivybridge_m_info = {
> @@ -297,6 +346,7 @@ static const struct intel_device_info intel_ivybridge_m_info = {
>  	.is_ivybridge = 1,
>  	.is_mobile = 1,
>  	.has_fbc = 1,
> +	GEN7_PIPEOFFSETS
>  };
>  
>  static const struct intel_device_info intel_ivybridge_q_info = {
> @@ -312,6 +362,7 @@ static const struct intel_device_info intel_valleyview_m_info = {
>  	.is_valleyview = 1,
>  	.display_mmio_offset = VLV_DISPLAY_BASE,
>  	.has_llc = 0, /* legal, last one wins */
> +	GEN_DEFAULT_PIPEOFFSETS
>  };
>  
>  static const struct intel_device_info intel_valleyview_d_info = {
> @@ -320,6 +371,7 @@ static const struct intel_device_info intel_valleyview_d_info = {
>  	.is_valleyview = 1,
>  	.display_mmio_offset = VLV_DISPLAY_BASE,
>  	.has_llc = 0, /* legal, last one wins */
> +	GEN_DEFAULT_PIPEOFFSETS
>  };
>  
>  static const struct intel_device_info intel_haswell_d_info = {
> @@ -328,6 +380,7 @@ static const struct intel_device_info intel_haswell_d_info = {
>  	.has_ddi = 1,
>  	.has_fpga_dbg = 1,
>  	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
> +	GEN7_PIPEOFFSETS
>  };
>  
>  static const struct intel_device_info intel_haswell_m_info = {
> @@ -338,6 +391,7 @@ static const struct intel_device_info intel_haswell_m_info = {
>  	.has_fpga_dbg = 1,
>  	.has_fbc = 1,
>  	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
> +	GEN7_PIPEOFFSETS
>  };
>  
>  static const struct intel_device_info intel_broadwell_d_info = {
> @@ -347,6 +401,7 @@ static const struct intel_device_info intel_broadwell_d_info = {
>  	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
>  	.has_llc = 1,
>  	.has_ddi = 1,
> +	GEN7_PIPEOFFSETS
>  };
>  
>  static const struct intel_device_info intel_broadwell_m_info = {
> @@ -356,6 +411,7 @@ static const struct intel_device_info intel_broadwell_m_info = {
>  	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
>  	.has_llc = 1,
>  	.has_ddi = 1,
> +	GEN7_PIPEOFFSETS
>  };
>  
>  /*
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index b98a7c8..7358b7b 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -66,7 +66,8 @@ enum transcoder {
>  	TRANSCODER_A = 0,
>  	TRANSCODER_B,
>  	TRANSCODER_C,
> -	TRANSCODER_EDP = 0xF,
> +	TRANSCODER_EDP,
> +	I915_MAX_TRANSCODERS
>  };
>  #define transcoder_name(t) ((t) + 'A')
>  
> @@ -492,6 +493,12 @@ struct intel_device_info {
>  	u8 gen;
>  	u8 ring_mask; /* Rings supported by the HW */
>  	DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG, SEP_SEMICOLON);
> +	/* Register offsets for the various display pipes */
> +	int pipe_offsets[I915_MAX_PIPES];
> +	int trans_offsets[I915_MAX_TRANSCODERS];
> +	int dpll_offsets[I915_MAX_PIPES];
> +	int dpll_md_offsets[I915_MAX_PIPES];
> +	int palette_offsets[I915_MAX_PIPES];
>  };
>  
>  #undef DEFINE_FLAG
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 849e595..0840c0a 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1198,6 +1198,9 @@
>  /*
>   * Clock control & power management
>   */
> +#define DPLL_A_OFFSET 0x6014
> +#define DPLL_B_OFFSET 0x6018
> +#define DPLL(pipe) (dev_priv->info->dpll_offsets[pipe])
>  
>  #define VGA0	0x6000
>  #define VGA1	0x6004
> @@ -1210,9 +1213,6 @@
>  #define   VGA1_PD_P1_DIV_2	(1 << 13)
>  #define   VGA1_PD_P1_SHIFT	8
>  #define   VGA1_PD_P1_MASK	(0x1f << 8)
> -#define _DPLL_A	(dev_priv->info->display_mmio_offset + 0x6014)
> -#define _DPLL_B	(dev_priv->info->display_mmio_offset + 0x6018)
> -#define DPLL(pipe) _PIPE(pipe, _DPLL_A, _DPLL_B)
>  #define   DPLL_VCO_ENABLE		(1 << 31)
>  #define   DPLL_SDVO_HIGH_SPEED		(1 << 30)
>  #define   DPLL_DVO_2X_MODE		(1 << 30)
> @@ -1274,7 +1274,10 @@
>  #define   SDVO_MULTIPLIER_MASK			0x000000ff
>  #define   SDVO_MULTIPLIER_SHIFT_HIRES		4
>  #define   SDVO_MULTIPLIER_SHIFT_VGA		0
> -#define _DPLL_A_MD (dev_priv->info->display_mmio_offset + 0x601c) /* 965+ only */
> +
> +#define DPLL_A_MD_OFFSET 0x601c /* 965+ only */
> +#define DPLL_B_MD_OFFSET 0x6020 /* 965+ only */
> +#define DPLL_MD(pipe) (dev_priv->info->dpll_md_offsets[pipe])
>  /*
>   * UDI pixel divider, controlling how many pixels are stuffed into a packet.
>   *
> @@ -1311,8 +1314,6 @@
>   */
>  #define   DPLL_MD_VGA_UDI_MULTIPLIER_MASK	0x0000003f
>  #define   DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT	0
> -#define _DPLL_B_MD (dev_priv->info->display_mmio_offset + 0x6020) /* 965+ only */
> -#define DPLL_MD(pipe) _PIPE(pipe, _DPLL_A_MD, _DPLL_B_MD)
>  
>  #define _FPA0	0x06040
>  #define _FPA1	0x06044
> @@ -1468,10 +1469,10 @@
>  /*
>   * Palette regs
>   */
> +#define PALETTE_A_OFFSET 0xa000
> +#define PALETTE_B_OFFSET 0xa800
>  
> -#define _PALETTE_A		(dev_priv->info->display_mmio_offset + 0xa000)
> -#define _PALETTE_B		(dev_priv->info->display_mmio_offset + 0xa800)
> -#define PALETTE(pipe) _PIPE(pipe, _PALETTE_A, _PALETTE_B)
> +#define PALETTE(pipe) (dev_priv->info->palette_offsets[pipe])
>  
>  /* MCH MMIO space */
>  
> @@ -1935,35 +1936,43 @@
>  	_PIPE_INC(pipe, _PIPE_CRC_RES_RES2_A_G4X, 0x01000)
>  
>  /* Pipe A timing regs */
> -#define _HTOTAL_A	(dev_priv->info->display_mmio_offset + 0x60000)
> -#define _HBLANK_A	(dev_priv->info->display_mmio_offset + 0x60004)
> -#define _HSYNC_A	(dev_priv->info->display_mmio_offset + 0x60008)
> -#define _VTOTAL_A	(dev_priv->info->display_mmio_offset + 0x6000c)
> -#define _VBLANK_A	(dev_priv->info->display_mmio_offset + 0x60010)
> -#define _VSYNC_A	(dev_priv->info->display_mmio_offset + 0x60014)
> -#define _PIPEASRC	(dev_priv->info->display_mmio_offset + 0x6001c)
> -#define _BCLRPAT_A	(dev_priv->info->display_mmio_offset + 0x60020)
> -#define _VSYNCSHIFT_A	(dev_priv->info->display_mmio_offset + 0x60028)
> +#define _HTOTAL_A	0x60000
> +#define _HBLANK_A	0x60004
> +#define _HSYNC_A	0x60008
> +#define _VTOTAL_A	0x6000c
> +#define _VBLANK_A	0x60010
> +#define _VSYNC_A	0x60014
> +#define _PIPEASRC	0x6001c
> +#define _BCLRPAT_A	0x60020
> +#define _VSYNCSHIFT_A	0x60028
>  
>  /* Pipe B timing regs */
> -#define _HTOTAL_B	(dev_priv->info->display_mmio_offset + 0x61000)
> -#define _HBLANK_B	(dev_priv->info->display_mmio_offset + 0x61004)
> -#define _HSYNC_B	(dev_priv->info->display_mmio_offset + 0x61008)
> -#define _VTOTAL_B	(dev_priv->info->display_mmio_offset + 0x6100c)
> -#define _VBLANK_B	(dev_priv->info->display_mmio_offset + 0x61010)
> -#define _VSYNC_B	(dev_priv->info->display_mmio_offset + 0x61014)
> -#define _PIPEBSRC	(dev_priv->info->display_mmio_offset + 0x6101c)
> -#define _BCLRPAT_B	(dev_priv->info->display_mmio_offset + 0x61020)
> -#define _VSYNCSHIFT_B	(dev_priv->info->display_mmio_offset + 0x61028)
> -
> -#define HTOTAL(trans) _TRANSCODER(trans, _HTOTAL_A, _HTOTAL_B)
> -#define HBLANK(trans) _TRANSCODER(trans, _HBLANK_A, _HBLANK_B)
> -#define HSYNC(trans) _TRANSCODER(trans, _HSYNC_A, _HSYNC_B)
> -#define VTOTAL(trans) _TRANSCODER(trans, _VTOTAL_A, _VTOTAL_B)
> -#define VBLANK(trans) _TRANSCODER(trans, _VBLANK_A, _VBLANK_B)
> -#define VSYNC(trans) _TRANSCODER(trans, _VSYNC_A, _VSYNC_B)
> -#define BCLRPAT(pipe) _PIPE(pipe, _BCLRPAT_A, _BCLRPAT_B)
> -#define VSYNCSHIFT(trans) _TRANSCODER(trans, _VSYNCSHIFT_A, _VSYNCSHIFT_B)
> +#define _HTOTAL_B	0x61000
> +#define _HBLANK_B	0x61004
> +#define _HSYNC_B	0x61008
> +#define _VTOTAL_B	0x6100c
> +#define _VBLANK_B	0x61010
> +#define _VSYNC_B	0x61014
> +#define _PIPEBSRC	0x6101c
> +#define _BCLRPAT_B	0x61020
> +#define _VSYNCSHIFT_B	0x61028
> +
> +#define TRANSCODER_A_OFFSET 0x60000
> +#define TRANSCODER_B_OFFSET 0x61000
> +#define TRANSCODER_C_OFFSET 0x62000
> +#define TRANSCODER_EDP_OFFSET 0x6f000
> +
> +#define _TRANSCODER2(pipe, reg) (dev_priv->info->trans_offsets[(pipe)] - \
> +	dev_priv->info->trans_offsets[TRANSCODER_A] + (reg))

Okay, I give up. I can't wrap my head around how TRANSCODER2 and PIPE2
macros are supposed to work. Care to explain for me a bit? Does the
substraction not drop the mmio offset out of the equation completely?

> +#define HTOTAL(trans) _TRANSCODER2(trans, _HTOTAL_A)
> +#define HBLANK(trans) _TRANSCODER2(trans, _HBLANK_A)
> +#define HSYNC(trans) _TRANSCODER2(trans, _HSYNC_A)
> +#define VTOTAL(trans) _TRANSCODER2(trans, _VTOTAL_A)
> +#define VBLANK(trans) _TRANSCODER2(trans, _VBLANK_A)
> +#define VSYNC(trans) _TRANSCODER2(trans, _VSYNC_A)
> +#define BCLRPAT(pipe) _PIPE2(pipe, _BCLRPAT_A)
> +#define VSYNCSHIFT(trans) _TRANSCODER2(trans, _VSYNCSHIFT_A)
>  
>  /* HSW+ eDP PSR registers */
>  #define EDP_PSR_BASE(dev)                       (IS_HASWELL(dev) ? 0x64800 : 0x6f800)
> @@ -3249,6 +3258,14 @@
>  #define   PIPE_VBLANK_INTERRUPT_STATUS		(1UL<<1)
>  #define   PIPE_OVERLAY_UPDATED_STATUS		(1UL<<0)
>  
> +#define PIPE_A_OFFSET	0x70000
> +#define PIPE_B_OFFSET	0x71000
> +#define PIPE_C_OFFSET	0x72000
> +#define PIPE_EDP_OFFSET	0x7f000

PIPE_EDP_OFFSET is unused.

> +
> +#define _PIPE2(pipe, reg) (dev_priv->info->pipe_offsets[(pipe)] - \
> +	dev_priv->info->pipe_offsets[PIPE_A] + (reg))
> +
>  #define PIPESRC(pipe) _PIPE(pipe, _PIPEASRC, _PIPEBSRC)
>  #define PIPECONF(tran) _TRANSCODER(tran, _PIPEACONF, _PIPEBCONF)
>  #define PIPEDSL(pipe)  _PIPE(pipe, _PIPEADSL, _PIPEBDSL)
> @@ -5869,4 +5886,14 @@
>  #define MIPI_READ_DATA_VALID(pipe)	_PIPE(pipe, _MIPIA_READ_DATA_VALID, _MIPIB_READ_DATA_VALID)
>  #define  READ_DATA_VALID(n)				(1 << (n))
>  
> +/* For UMS only (deprecated): */
> +#define _PALETTE_A (dev_priv->info->display_mmio_offset + 0xa000)
> +#define _PALETTE_B (dev_priv->info->display_mmio_offset + 0xa800)
> +#define _DPLL_A (dev_priv->info->display_mmio_offset + 0x6014)
> +#define _DPLL_B (dev_priv->info->display_mmio_offset + 0x6018)
> +#define _DPLL_A_MD (dev_priv->info->display_mmio_offset + 0x601c)
> +#define _DPLL_B_MD (dev_priv->info->display_mmio_offset + 0x6020)
> +#define _PALETTE_A (dev_priv->info->display_mmio_offset + 0xa000)
> +#define _PALETTE_B (dev_priv->info->display_mmio_offset + 0xa800)

Palettes defined twice.

> +
>  #endif /* _I915_REG_H_ */
> -- 
> 1.8.1.5
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Jani Nikula, Intel Open Source Technology Center

      reply	other threads:[~2013-12-04 15:27 UTC|newest]

Thread overview: 2+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2013-11-27 13:45 [RFC v2] drm/i915: Clean up display pipe register accesses Antti Koskipaa
2013-12-04 15:24 ` Jani Nikula [this message]

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