Re: [RFC] SystemACE driver - abstract register ops

[Peter Korsgaard <peter.korsgaard@barco.com>]

>>>>> "WR" == Wolfgang Reissnegger <wolfgang.reissnegger@xilinx.com> writes:

Hi,

WR> The end goal is to have a kernel tree that contains ALL Xilinx
WR> drivers and the multitude of drivers that are being
WR> created/updated and contributed here. Having such a kernel
WR> available will simplify the process of bringing up a new
WR> system. The hope is that contributors will adopt the idea of
WR> having a "Xilinx" kernel and will start using that tree as a "base
WR> reference".

But there already is such a tree - It's called 'mainline'. I can see
some advantage in having a Xilinx tree as a staging area, but it
really HAS to be a temporary thing and stuff needs to be pushed to
mainline.

WR> I will post news here as they unfold. In the meantime it would be
WR> very interesting to hear ideas and suggestions from you. Concerns
WR> that people have. Pitfalls to look out for etc.

Hereby my 2 cents.

-- 
Bye, Peter Korsgaard