From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D07D9C5AD7B for ; Mon, 10 Aug 2026 22:37:04 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 7C2F410EA01; Mon, 10 Aug 2026 22:37:04 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="NismwQlj"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.18]) by gabe.freedesktop.org (Postfix) with ESMTPS id D533110EA01 for ; Mon, 10 Aug 2026 22:37:02 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1786401423; x=1817937423; h=date:message-id:from:to:cc:subject:in-reply-to: references:mime-version; bh=7AicYmvxAT4dXAbJ8afyGgW79WCoVjKcKLyMWbF2xnI=; b=NismwQlj2zfFnCBwd0jML1jkFa+6l9125QI7WXjlEwSn/1S9/pjbZNqq 8AR5qVlEEYkYcS2L2UJtZ8igeJYxrzY2oI9NCeV2GibuMMZ4+S+HMsra7 90gegk7wMSNRmSi4Dv1lnKyuxpHX3OSMe0h4Yf/iJBqXe+CYrNuxxXTnW uE3eXKuBlquVIIxNZkIla2IZcfvwQdDu6Aga+8Ja54qcoEH0bEnAvDm4Z teO7cU/MixKV6TDRUcCXFrCkTCVhX32qWKObTIUPV+nJkCdgwlxjTPKb9 teusy7KZVy/L+HCDmbt/WEIoglXN8zLoVFTNk0za5qhFUBkL+iwWkQCY9 g==; X-CSE-ConnectionGUID: Cs1gP9twRx6TyJSYhbhITw== X-CSE-MsgGUID: 3fHJRlWXSb6THuo0+NmYGQ== X-IronPort-AV: E=McAfee;i="6800,10657,11871"; a="87001286" X-IronPort-AV: E=Sophos;i="6.25,216,1779174000"; d="scan'208";a="87001286" Received: from orviesa006.jf.intel.com ([10.64.159.146]) by orvoesa110.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Aug 2026 15:37:03 -0700 X-CSE-ConnectionGUID: /qQTE9reQiSLm9MjkNrt0A== X-CSE-MsgGUID: F6s772ZlRvq41C45Qqom2w== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.25,216,1779174000"; d="scan'208";a="261413054" Received: from unknown (HELO adixit-MOBL3.intel.com) ([10.241.243.70]) by orviesa006-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Aug 2026 15:37:03 -0700 Date: Mon, 10 Aug 2026 15:37:02 -0700 Message-ID: <87ecg5hab5.wl-ashutosh.dixit@intel.com> From: "Dixit, Ashutosh" To: Umesh Nerlige Ramappa Cc: Subject: Re: [PATCH 1/3] drm/xe/xe_oa: Clear status only if relevant bits are set In-Reply-To: <20260806224702.3563031-6-umesh.nerlige.ramappa@intel.com> References: <20260806224702.3563031-5-umesh.nerlige.ramappa@intel.com> <20260806224702.3563031-6-umesh.nerlige.ramappa@intel.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?ISO-8859-4?Q?Goj=F2?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/30.2 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-BeenThere: intel-xe@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel Xe graphics driver List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-xe-bounces@lists.freedesktop.org Sender: "Intel-xe" On Thu, 06 Aug 2026 15:47:04 -0700, Umesh Nerlige Ramappa wrote: > > OA monitors only a few bits in the status field. The current > read-modify-write will write to the MMIO even if none of the relevant > bits are set. Clear the status only if relevant bits are set. > > Signed-off-by: Umesh Nerlige Ramappa > --- > drivers/gpu/drm/xe/xe_oa.c | 8 +++++--- > 1 file changed, 5 insertions(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/xe/xe_oa.c b/drivers/gpu/drm/xe/xe_oa.c > index cb526de0ef87..183956170757 100644 > --- a/drivers/gpu/drm/xe/xe_oa.c > +++ b/drivers/gpu/drm/xe/xe_oa.c > @@ -543,14 +543,16 @@ static int __xe_oa_read(struct xe_oa_stream *stream, char __user *buf, > size_t count, size_t *offset) > { > /* Only clear our bits to avoid side-effects */ > - stream->oa_status = xe_mmio_rmw32(&stream->gt->mmio, __oa_regs(stream)->oa_status, > - OASTATUS_RELEVANT_BITS, 0); > + stream->oa_status = xe_mmio_read32(&stream->gt->mmio, __oa_regs(stream)->oa_status); > /* > * Signal to userspace that there is non-zero OA status to read via > * @DRM_XE_OBSERVATION_IOCTL_STATUS observation stream fd ioctl > */ > - if (stream->oa_status & OASTATUS_RELEVANT_BITS) > + if (stream->oa_status & OASTATUS_RELEVANT_BITS) { > + xe_mmio_write32(&stream->gt->mmio, __oa_regs(stream)->oa_status, > + stream->oa_status & ~OASTATUS_RELEVANT_BITS); Hmm, because pcie reads are expensive, and pcie writes are posted writes, how much difference is this really going to make? Anyway, if you still want to merge this, move the comment /* Only clear our bits to avoid side-effects */ above this line. With that, this is: Reviewed-by: Ashutosh Dixit > return -EIO; > + } > > return xe_oa_append_reports(stream, buf, count, offset); > } > -- > 2.51.0 >