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From: Gustavo Sousa <gustavo.sousa@intel.com>
To: <I915-ci-infra@lists.freedesktop.org>
Cc: <intel-xe@lists.freedesktop.org>
Subject: Re: ✗ Xe.CI.FULL: failure for Extra enabling patches for NVL-P (rev5)
Date: Tue, 10 Mar 2026 19:09:22 -0300	[thread overview]
Message-ID: <87eclrwd4d.fsf@intel.com> (raw)
In-Reply-To: <177312554403.336878.17311247628327327824@a3b018990fe9>

Patchwork <patchwork@emeril.freedesktop.org> writes:

> == Series Details ==
>
> Series: Extra enabling patches for NVL-P (rev5)
> URL   : https://patchwork.freedesktop.org/series/162666/
> State : failure
>
> == Summary ==
>
> CI Bug Log - changes from xe-4684-6fb391baa6059adc4a8e75765a1ebf64868fc1a9_FULL -> xe-pw-162666v5_FULL
> ====================================================
>
> Summary
> -------
>
>   **FAILURE**
>
>   Serious unknown changes coming with xe-pw-162666v5_FULL absolutely need to be
>   verified manually.
>   
>   If you think the reported changes have nothing to do with the changes
>   introduced in xe-pw-162666v5_FULL, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
>   to document this new failure mode, which will reduce false positives in CI.
>
>   
>
> Participating hosts (2 -> 2)
> ------------------------------
>
>   No changes in participating hosts
>
> Possible new issues
> -------------------
>
>   Here are the unknown changes that may have been introduced in xe-pw-162666v5_FULL:
>
> ### IGT changes ###
>
> #### Possible regressions ####
>
>   * igt@kms_plane_cursor@primary@pipe-a-dp-2-size-128:
>     - shard-bmg:          [PASS][1] -> [DMESG-FAIL][2]
>    [1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4684-6fb391baa6059adc4a8e75765a1ebf64868fc1a9/shard-bmg-7/igt@kms_plane_cursor@primary@pipe-a-dp-2-size-128.html
>    [2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-162666v5/shard-bmg-2/igt@kms_plane_cursor@primary@pipe-a-dp-2-size-128.html

This "GuC Crash dump notification" erro appears to be a sporadic
issue that has been happening on the shard-bmg-2 machine but not
captured in CBL yet.  Some other examples:

    https://intel-gfx-ci.01.org/tree/intel-xe/xe-4673-79792a2fc5d37b5446e543f1de05158ab0f551c9/shard-bmg-2/igt@kms_flip@plain-flip-fb-recreate@c-dp2.html
    https://intel-gfx-ci.01.org/tree/intel-xe/xe-4663-d5f492dbc8c65c78ee639fa06821eeb568c547cb/shard-bmg-2/igt@kms_flip@flip-vs-modeset-vs-hang.html
    https://intel-gfx-ci.01.org/tree/intel-xe/xe-4663-d5f492dbc8c65c78ee639fa06821eeb568c547cb/shard-bmg-2/igt@kms_flip@flip-vs-modeset-vs-hang@a-dp2.html
    https://intel-gfx-ci.01.org/tree/intel-xe/xe-4631-eb7d0d7fa26e755dba8653a594563ce027641d69/shard-bmg-2/igt@kms_flip@modeset-vs-vblank-race@c-hdmi-a3.html
    https://intel-gfx-ci.01.org/tree/intel-xe/xe-4616-98bd1343bd71df415eafe65885b941d96a2c06cf/shard-bmg-2/igt@kms_color@degamma@pipe-c-hdmi-a-3.html
    https://intel-gfx-ci.01.org/tree/intel-xe/xe-4616-98bd1343bd71df415eafe65885b941d96a2c06cf/shard-bmg-2/igt@kms_color@degamma.html
    https://intel-gfx-ci.01.org/tree/intel-xe/xe-4588-cec43d5c2696af219fc2ef71dd7e93db48c80f66/shard-bmg-2/igt@kms_flip@2x-flip-vs-dpms-off-vs-modeset-interruptible@bc-dp2-hdmi-a3.html
    https://intel-gfx-ci.01.org/tree/intel-xe/xe-4579-84d640df1ee7e526fd84de4cc1b8bb1e9d391ee1/shard-bmg-2/igt@kms_atomic_transition@modeset-transition-nonblocking-fencing.html
    https://intel-gfx-ci.01.org/tree/intel-xe/xe-4579-84d640df1ee7e526fd84de4cc1b8bb1e9d391ee1/shard-bmg-2/igt@kms_atomic_transition@modeset-transition-nonblocking-fencing@1x-outputs.html
    https://intel-gfx-ci.01.org/tree/intel-xe/xe-4568-15658979e64a7c97eaa65563e27a5a65e68a0188/shard-bmg-2/igt@kms_atomic_transition@plane-all-modeset-transition-fencing@pipe-a-dp-2.html
    https://intel-gfx-ci.01.org/tree/intel-xe/xe-4520-ab5b6da7d4879640bce3197597e0bc707bd60ab5/shard-bmg-2/igt@kms_atomic_transition@plane-all-transition-nonblocking@pipe-a-dp-2.html
    https://intel-gfx-ci.01.org/tree/intel-xe/xe-4520-ab5b6da7d4879640bce3197597e0bc707bd60ab5/shard-bmg-2/igt@kms_atomic_transition@plane-all-transition-nonblocking.html
    https://intel-gfx-ci.01.org/tree/intel-xe/xe-4519-d9124a6be3c7bdaeb14c3629013dde27929dbf04/shard-bmg-2/igt@kms_bw@connected-linear-tiling-1-displays-1920x1080p.html
    https://intel-gfx-ci.01.org/tree/intel-xe/xe-4496-ff449f153b0966cfd7a7291670c927f6b6971d2a/shard-bmg-2/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-xr24@pipe-d-dp-2.html
    https://intel-gfx-ci.01.org/tree/intel-xe/xe-4496-ff449f153b0966cfd7a7291670c927f6b6971d2a/shard-bmg-2/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-xr24.html
    https://intel-gfx-ci.01.org/tree/intel-xe/xe-4475-69c1143407ca17d556eb4e5ead7eb43b60a3fe65/shard-bmg-2/igt@xe_exec_system_allocator@once-large-mmap-new.html
    https://intel-gfx-ci.01.org/tree/intel-xe/xe-4475-69c1143407ca17d556eb4e5ead7eb43b60a3fe65/shard-bmg-2/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-hflip.html
    https://intel-gfx-ci.01.org/tree/intel-xe/xe-4444-412ff4e2efa281effa1f5be5c610838d151380cc/shard-bmg-2/igt@kms_color@ctm-0-25@pipe-c-dp-2.html
    https://intel-gfx-ci.01.org/tree/intel-xe/xe-4444-412ff4e2efa281effa1f5be5c610838d151380cc/shard-bmg-2/igt@kms_color@ctm-0-25.html
    https://intel-gfx-ci.01.org/tree/intel-xe/xe-4402-1956fa9bd80d606f7eb92e877680de38a4f6e8ef/shard-bmg-2/igt@xe_exec_fault_mode@many-bindexecqueue-userptr-invalidate-race-prefetch.html
    https://intel-gfx-ci.01.org/tree/intel-xe/xe-4346-d7d19ebd62e1a312e67f4484df9a4e2b407d93d0/shard-bmg-2/igt@xe_exec_system_allocator@twice-malloc-mlock-nomemset.html

This is unrelated to this series.

--
Gustavo Sousa

  reply	other threads:[~2026-03-10 22:09 UTC|newest]

Thread overview: 13+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-03-10  0:42 [PATCH v5 0/7] Extra enabling patches for NVL-P Gustavo Sousa
2026-03-10  0:42 ` [PATCH v5 1/7] drm/xe: Modify stepping info directly in xe_step_*_get() Gustavo Sousa
2026-03-10  0:42 ` [PATCH v5 2/7] drm/xe: Drop unused IS_PLATFORM_STEP() and IS_SUBPLATFORM_STEP() Gustavo Sousa
2026-03-10  0:42 ` [PATCH v5 3/7] drm/xe/nvlp: Read platform-level stepping info Gustavo Sousa
2026-03-10  0:42 ` [PATCH v5 4/7] drm/xe/rtp: Add support for matching platform-level stepping Gustavo Sousa
2026-03-10  0:42 ` [PATCH v5 5/7] drm/xe/nvlp: Implement Wa_14026539277 Gustavo Sousa
2026-03-10  0:42 ` [PATCH v5 6/7] drm/xe/xe3p: Drop Wa_16028780921 Gustavo Sousa
2026-03-10  0:42 ` [PATCH v5 7/7] drm/xe: Translate C-state "reset value" into RC6 Gustavo Sousa
2026-03-10  0:50 ` ✓ CI.KUnit: success for Extra enabling patches for NVL-P (rev5) Patchwork
2026-03-10  1:51 ` ✓ Xe.CI.BAT: " Patchwork
2026-03-10  6:52 ` ✗ Xe.CI.FULL: failure " Patchwork
2026-03-10 22:09   ` Gustavo Sousa [this message]
2026-03-10 23:10 ` [PATCH v5 0/7] Extra enabling patches for NVL-P Gustavo Sousa

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