Re: [patch 12/12] x86/cacheinfo.c: check for block interference CPUs

[Thomas Gleixner <tglx@linutronix.de>]

On Tue, Feb 06 2024 at 15:49, Marcelo Tosatti wrote:
> @@ -396,6 +397,7 @@ static void amd_l3_disable_index(struct
>  	 *  disable index in all 4 subcaches
>  	 */
>  	for (i = 0; i < 4; i++) {
> +		int ret;
>  		u32 reg = idx | (i << 20);
>  
>  		if (!nb->l3_cache.subcaches[i])
> @@ -409,6 +411,7 @@ static void amd_l3_disable_index(struct
>  		 * is not sufficient.
>  		 */
>  		ret = wbinvd_on_cpu(cpu);
> +		WARN_ON(ret == -EPERM);

What? You create inconsistent state here.

> -	amd_l3_disable_index(nb, cpu, slot, index);
> +	ret = 0;
> +	idx = block_interf_srcu_read_lock();
> +
> +	if (block_interf_cpu(cpu))
> +		ret = -EPERM;
> +	else
> +		amd_l3_disable_index(nb, cpu, slot, index);
> +
> +	block_interf_srcu_read_unlock(idx);

Again. This is a root only operation.

This whole patch series is just voodoo programming with zero
justification for the mess it creates.

Thanks,

        tglx
.