From: Fabiano Rosas <farosas@suse.de>
To: Nicholas Piggin <npiggin@gmail.com>, qemu-ppc@nongnu.org
Cc: Nicholas Piggin <npiggin@gmail.com>,
qemu-devel@nongnu.org,
Daniel Henrique Barboza <danielhb413@gmail.com>
Subject: Re: [PATCH v2 5/6] target/ppc: Add SRR1 prefix indication to interrupt handlers
Date: Fri, 31 Mar 2023 18:26:12 -0300 [thread overview]
Message-ID: <87edp4zk7f.fsf@suse.de> (raw)
In-Reply-To: <20230327131218.2721044-5-npiggin@gmail.com>
Nicholas Piggin <npiggin@gmail.com> writes:
> ISA v3.1 introduced prefix instructions. Among the changes, various
> synchronous interrupts report whether they were caused by a prefix
> instruction in (H)SRR1.
>
> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Reviewed-by: Fabiano Rosas <farosas@suse.de>
next prev parent reply other threads:[~2023-03-31 21:26 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-03-27 13:12 [PATCH v2 1/6] target/ppc: Fix width of some 32-bit SPRs Nicholas Piggin
2023-03-27 13:12 ` [PATCH v2 2/6] target/ppc: Better CTRL SPR implementation Nicholas Piggin
2023-03-27 13:12 ` [PATCH v2 3/6] target/ppc: Fix instruction loading endianness in alignment interrupt Nicholas Piggin
2023-03-31 21:27 ` Fabiano Rosas
2023-05-23 18:11 ` Anushree Mathur
2023-03-27 13:12 ` [PATCH v2 4/6] target/ppc: Alignment faults do not set DSISR in ISA v3.0 onward Nicholas Piggin
2023-03-31 21:25 ` Fabiano Rosas
2023-03-27 13:12 ` [PATCH v2 5/6] target/ppc: Add SRR1 prefix indication to interrupt handlers Nicholas Piggin
2023-03-31 21:26 ` Fabiano Rosas [this message]
2023-03-27 13:12 ` [PATCH v2 6/6] target/ppc: Implement HEIR SPR Nicholas Piggin
2023-03-29 5:51 ` Michael Neuling
2023-04-02 2:48 ` Nicholas Piggin
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