From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6244AC6FA82 for ; Tue, 13 Sep 2022 13:55:59 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id C818D10E71D; Tue, 13 Sep 2022 13:55:57 +0000 (UTC) Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by gabe.freedesktop.org (Postfix) with ESMTPS id 4071E10E71D for ; Tue, 13 Sep 2022 13:55:54 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1663077354; x=1694613354; h=from:to:cc:subject:in-reply-to:references:date: message-id:mime-version; bh=0pLrTyDx2j/9/LwBYAI3L3kInQeaOWfE2j6nAt1bu/c=; b=RkhBfbs5w5oLVGMXBJlCXXLm+gcdhVNV0W4tpFUQ3zTO5RYLr19HGvbW DSoMNZOeGCqmsOofe5LKaQeqNiuwUNbFbaTyJy864a4O7O4Fh57+wmepf 9WAPauaVEj+Xp8yNAITpR1CRMJ8zqVqOoJGa/VRI7mZFfyEsjqhFzwr34 VYvC+rLvpgUwMcctT+4aJSsi1Kqk6dUDWQxj0BWcZ/m/c+g6pTOhR3AeU sWotk64yzSsmY961hYPbseg495ftCyCk56JTIXnx5aemFCINY8FGyIo7p 0zXuwnpHWBFGclzmh5bmZCt9FomU98S23UOpw7UaEoNE+scVinZdiCybN g==; X-IronPort-AV: E=McAfee;i="6500,9779,10469"; a="299479969" X-IronPort-AV: E=Sophos;i="5.93,312,1654585200"; d="scan'208";a="299479969" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Sep 2022 06:55:53 -0700 X-IronPort-AV: E=Sophos;i="5.93,312,1654585200"; d="scan'208";a="678576766" Received: from baumeish-mobl.ger.corp.intel.com (HELO localhost) ([10.252.59.168]) by fmsmga008-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Sep 2022 06:55:51 -0700 From: Jani Nikula To: Ankit Nautiyal , dri-devel@lists.freedesktop.org Subject: Re: [PATCH 3/4] drm/edid: Refactor HFVSDB parsing for DSC1.2 In-Reply-To: <20220811054718.2115917-4-ankit.k.nautiyal@intel.com> Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo References: <20220811054718.2115917-1-ankit.k.nautiyal@intel.com> <20220811054718.2115917-4-ankit.k.nautiyal@intel.com> Date: Tue, 13 Sep 2022 16:55:46 +0300 Message-ID: <87edwf4bvh.fsf@intel.com> MIME-Version: 1.0 Content-Type: text/plain X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: uma.shankar@intel.com, maarten.lankhorst@intel.com, swati2.sharma@intel.com Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" On Thu, 11 Aug 2022, Ankit Nautiyal wrote: > DSC capabilities are given in bytes 11-13 of VSDB (i.e. bytes 8-10 of > SCDS). Since minimum length of Data block is 7, all bytes greater than 7 > must be read only after checking the length of the data block. > > This patch adds check for data block length before reading relavant DSC > bytes. > > Signed-off-by: Ankit Nautiyal Reviewed-by: Jani Nikula > --- > drivers/gpu/drm/drm_edid.c | 93 ++++++++++++++++++++------------------ > 1 file changed, 49 insertions(+), 44 deletions(-) > > diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c > index ffff1d08b3a4..c9c3a9c8fa26 100644 > --- a/drivers/gpu/drm/drm_edid.c > +++ b/drivers/gpu/drm/drm_edid.c > @@ -5706,9 +5706,6 @@ static void drm_parse_ycbcr420_deep_color_info(struct drm_connector *connector, > static void drm_parse_dsc_info(struct drm_hdmi_dsc_cap *hdmi_dsc, > const u8 *hf_scds) > { > - u8 dsc_max_slices; > - u8 dsc_max_frl_rate; > - > hdmi_dsc->v_1p2 = hf_scds[11] & DRM_EDID_DSC_1P2; > > if (!hdmi_dsc->v_1p2) > @@ -5727,47 +5724,54 @@ static void drm_parse_dsc_info(struct drm_hdmi_dsc_cap *hdmi_dsc, > /* Supports min 8 BPC if DSC1.2 is supported*/ > hdmi_dsc->bpc_supported = 8; > > - dsc_max_frl_rate = (hf_scds[12] & DRM_EDID_DSC_MAX_FRL_RATE_MASK) >> 4; > - drm_get_max_frl_rate(dsc_max_frl_rate, &hdmi_dsc->max_lanes, > - &hdmi_dsc->max_frl_rate_per_lane); > - hdmi_dsc->total_chunk_kbytes = hf_scds[13] & DRM_EDID_DSC_TOTAL_CHUNK_KBYTES; > + if (cea_db_payload_len(hf_scds) >= 12 && hf_scds[12]) { > + u8 dsc_max_slices; > + u8 dsc_max_frl_rate; > > - dsc_max_slices = hf_scds[12] & DRM_EDID_DSC_MAX_SLICES; > + dsc_max_frl_rate = (hf_scds[12] & DRM_EDID_DSC_MAX_FRL_RATE_MASK) >> 4; > + drm_get_max_frl_rate(dsc_max_frl_rate, &hdmi_dsc->max_lanes, > + &hdmi_dsc->max_frl_rate_per_lane); > > - switch (dsc_max_slices) { > - case 1: > - hdmi_dsc->max_slices = 1; > - hdmi_dsc->clk_per_slice = 340; > - break; > - case 2: > - hdmi_dsc->max_slices = 2; > - hdmi_dsc->clk_per_slice = 340; > - break; > - case 3: > - hdmi_dsc->max_slices = 4; > - hdmi_dsc->clk_per_slice = 340; > - break; > - case 4: > - hdmi_dsc->max_slices = 8; > - hdmi_dsc->clk_per_slice = 340; > - break; > - case 5: > - hdmi_dsc->max_slices = 8; > - hdmi_dsc->clk_per_slice = 400; > - break; > - case 6: > - hdmi_dsc->max_slices = 12; > - hdmi_dsc->clk_per_slice = 400; > - break; > - case 7: > - hdmi_dsc->max_slices = 16; > - hdmi_dsc->clk_per_slice = 400; > - break; > - case 0: > - default: > - hdmi_dsc->max_slices = 0; > - hdmi_dsc->clk_per_slice = 0; > + dsc_max_slices = hf_scds[12] & DRM_EDID_DSC_MAX_SLICES; > + > + switch (dsc_max_slices) { > + case 1: > + hdmi_dsc->max_slices = 1; > + hdmi_dsc->clk_per_slice = 340; > + break; > + case 2: > + hdmi_dsc->max_slices = 2; > + hdmi_dsc->clk_per_slice = 340; > + break; > + case 3: > + hdmi_dsc->max_slices = 4; > + hdmi_dsc->clk_per_slice = 340; > + break; > + case 4: > + hdmi_dsc->max_slices = 8; > + hdmi_dsc->clk_per_slice = 340; > + break; > + case 5: > + hdmi_dsc->max_slices = 8; > + hdmi_dsc->clk_per_slice = 400; > + break; > + case 6: > + hdmi_dsc->max_slices = 12; > + hdmi_dsc->clk_per_slice = 400; > + break; > + case 7: > + hdmi_dsc->max_slices = 16; > + hdmi_dsc->clk_per_slice = 400; > + break; > + case 0: > + default: > + hdmi_dsc->max_slices = 0; > + hdmi_dsc->clk_per_slice = 0; > + } > } > + > + if (cea_db_payload_len(hf_scds) >= 13 && hf_scds[13]) > + hdmi_dsc->total_chunk_kbytes = hf_scds[13] & DRM_EDID_DSC_TOTAL_CHUNK_KBYTES; > } > > /* Sink Capability Data Structure */ > @@ -5776,6 +5780,7 @@ static void drm_parse_hdmi_forum_scds(struct drm_connector *connector, > { > struct drm_display_info *display = &connector->display_info; > struct drm_hdmi_info *hdmi = &display->hdmi; > + struct drm_hdmi_dsc_cap *hdmi_dsc = &hdmi->dsc_cap; > > display->has_hdmi_infoframe = true; > > @@ -5816,17 +5821,17 @@ static void drm_parse_hdmi_forum_scds(struct drm_connector *connector, > > if (hf_scds[7]) { > u8 max_frl_rate; > - struct drm_hdmi_dsc_cap *hdmi_dsc = &hdmi->dsc_cap; > > DRM_DEBUG_KMS("hdmi_21 sink detected. parsing edid\n"); > max_frl_rate = (hf_scds[7] & DRM_EDID_MAX_FRL_RATE_MASK) >> 4; > drm_get_max_frl_rate(max_frl_rate, &hdmi->max_lanes, > &hdmi->max_frl_rate_per_lane); > - > - drm_parse_dsc_info(hdmi_dsc, hf_scds); > } > > drm_parse_ycbcr420_deep_color_info(connector, hf_scds); > + > + if (cea_db_payload_len(hf_scds) >= 11 && hf_scds[11]) > + drm_parse_dsc_info(hdmi_dsc, hf_scds); > } > > static void drm_parse_hdmi_deep_color_info(struct drm_connector *connector, -- Jani Nikula, Intel Open Source Graphics Center