From: Jani Nikula <jani.nikula@linux.intel.com>
To: Uma Shankar <uma.shankar@intel.com>, intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH v2 2/3] drm/i915/xelpd: Enable Pipe Degamma
Date: Mon, 29 Nov 2021 18:19:52 +0200 [thread overview]
Message-ID: <87ee6zj5nb.fsf@intel.com> (raw)
In-Reply-To: <20211125202750.3263848-3-uma.shankar@intel.com>
On Fri, 26 Nov 2021, Uma Shankar <uma.shankar@intel.com> wrote:
> Enable Pipe Degamma for XE_LPD. Extend the legacy implementation
> to incorparate the extended lut size for XE_LPD.
>
> v2: Added a helper for degamma lut size (Ville)
>
> Signed-off-by: Uma Shankar <uma.shankar@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_color.c | 14 +++++++++++---
> 1 file changed, 11 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
> index 42fe549ef6fe..de3ded1e327a 100644
> --- a/drivers/gpu/drm/i915/display/intel_color.c
> +++ b/drivers/gpu/drm/i915/display/intel_color.c
> @@ -808,6 +808,14 @@ static void bdw_load_luts(const struct intel_crtc_state *crtc_state)
> }
> }
>
> +static int glk_degamma_lut_size(struct drm_i915_private *i915)
> +{
> + if (DISPLAY_VER(i915) >= 13)
> + return 131;
> + else
> + return 35;
> +}
> +
Why do we have both a function with hardcoded values and device info
members for this?
BR,
Jani.
> static void glk_load_degamma_lut(const struct intel_crtc_state *crtc_state)
> {
> struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> @@ -827,8 +835,8 @@ static void glk_load_degamma_lut(const struct intel_crtc_state *crtc_state)
>
> for (i = 0; i < lut_size; i++) {
> /*
> - * First 33 entries represent range from 0 to 1.0
> - * 34th and 35th entry will represent extended range
> + * First lut_size entries represent range from 0 to 1.0
> + * 3 additional lut entries will represent extended range
> * inputs 3.0 and 7.0 respectively, currently clamped
> * at 1.0. Since the precision is 16bit, the user
> * value can be directly filled to register.
> @@ -844,7 +852,7 @@ static void glk_load_degamma_lut(const struct intel_crtc_state *crtc_state)
> }
>
> /* Clamp values > 1.0. */
> - while (i++ < 35)
> + while (i++ < glk_degamma_lut_size(dev_priv))
> intel_de_write_fw(dev_priv, PRE_CSC_GAMC_DATA(pipe), 1 << 16);
>
> intel_de_write_fw(dev_priv, PRE_CSC_GAMC_INDEX(pipe), 0);
--
Jani Nikula, Intel Open Source Graphics Center
next prev parent reply other threads:[~2021-11-29 16:21 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-11-25 20:27 [Intel-gfx] [PATCH v2 0/3] Enable pipe color support on D13 platform Uma Shankar
2021-11-25 20:27 ` [Intel-gfx] [PATCH v2 1/3] drm/i915/xelpd: Enable Pipe color support for " Uma Shankar
2021-11-25 20:27 ` [Intel-gfx] [PATCH v2 2/3] drm/i915/xelpd: Enable Pipe Degamma Uma Shankar
2021-11-29 16:19 ` Jani Nikula [this message]
2021-11-30 10:01 ` Ville Syrjälä
2021-11-30 10:06 ` Jani Nikula
2021-12-07 6:45 ` Shankar, Uma
2021-11-30 10:04 ` Ville Syrjälä
2021-11-25 20:27 ` [Intel-gfx] [PATCH v2 3/3] drm/i915/xelpd: Add Pipe Color Lut caps to platform config Uma Shankar
2021-11-30 10:03 ` Ville Syrjälä
2021-12-07 6:46 ` Shankar, Uma
2021-11-25 21:37 ` [Intel-gfx] ✓ Fi.CI.BAT: success for Enable pipe color support on D13 platform (rev2) Patchwork
2021-11-26 4:51 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
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