From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.0 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A81F2C04AB1 for ; Mon, 13 May 2019 05:59:31 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 1897A20879 for ; Mon, 13 May 2019 05:59:30 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 1897A20879 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=users.sourceforge.jp Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Received: from localhost ([127.0.0.1]:51524 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hQ3zm-0007vT-4B for qemu-devel@archiver.kernel.org; Mon, 13 May 2019 01:59:30 -0400 Received: from eggs.gnu.org ([209.51.188.92]:60375) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hQ3yR-000726-AB for qemu-devel@nongnu.org; Mon, 13 May 2019 01:58:09 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hQ3yO-0003fa-TL for qemu-devel@nongnu.org; Mon, 13 May 2019 01:58:07 -0400 Received: from mail03.asahi-net.or.jp ([202.224.55.15]:60161) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hQ3yO-0003ef-Fn for qemu-devel@nongnu.org; Mon, 13 May 2019 01:58:04 -0400 Received: from h61-195-96-97.vps.ablenet.jp (h61-195-96-97.vps.ablenet.jp [61.195.96.97]) (Authenticated sender: PQ4Y-STU) by mail03.asahi-net.or.jp (Postfix) with ESMTPA id 9702741946; Mon, 13 May 2019 14:58:01 +0900 (JST) Received: from yo-satoh-debian.ysato.ml (ZM005235.ppp.dion.ne.jp [222.8.5.235]) by h61-195-96-97.vps.ablenet.jp (Postfix) with ESMTPSA id 126A9240085; Mon, 13 May 2019 14:58:00 +0900 (JST) Date: Mon, 13 May 2019 14:57:59 +0900 Message-ID: <87ef52521k.wl-ysato@users.sourceforge.jp> From: Yoshinori Sato To: Philippe =?ISO-8859-1?Q?Mathieu-Daud=E9?= In-Reply-To: References: <20190508145611.107133-1-ysato@users.sourceforge.jp> <20190508145611.107133-7-ysato@users.sourceforge.jp> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM/1.14.9 (=?ISO-8859-4?Q?Goj=F2?=) APEL/10.8 EasyPG/1.0.0 Emacs/25.1 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 202.224.55.15 Subject: Re: [Qemu-devel] [PATCH v10 06/13] hw/intc: RX62N interrupt controller (ICUa) X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, richard.henderson@linaro.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On Thu, 09 May 2019 01:27:40 +0900, Philippe Mathieu-Daud=E9 wrote: >=20 > On 5/8/19 4:56 PM, Yoshinori Sato wrote: > > This implementation supported only ICUa. > > Hardware manual. > > https://www.renesas.com/us/en/doc/products/mpumcu/doc/rx_family/r01uh00= 33ej0140_rx62n.pdf > >=20 > > Signed-off-by: Yoshinori Sato > > --- > > include/hw/intc/rx_icu.h | 49 +++++++ > > hw/intc/rx_icu.c | 375 +++++++++++++++++++++++++++++++++++++++= ++++++++ > > hw/intc/Makefile.objs | 1 + > > 3 files changed, 425 insertions(+) > > create mode 100644 include/hw/intc/rx_icu.h > > create mode 100644 hw/intc/rx_icu.c > >=20 > > diff --git a/include/hw/intc/rx_icu.h b/include/hw/intc/rx_icu.h > > new file mode 100644 > > index 0000000000..bc46b3079b > > --- /dev/null > > +++ b/include/hw/intc/rx_icu.h > > @@ -0,0 +1,49 @@ > > +#ifndef RX_ICU_H > > +#define RX_ICU_H > > + > > +#include "qemu-common.h" > > +#include "hw/irq.h" > > + > > +struct IRQSource { > > + int sense; >=20 > Hmm can you use the enum? >=20 > > + int level; > > +}; > > + > > +struct RXICUState { > > + SysBusDevice parent_obj; > > + > > + MemoryRegion memory; > > + struct IRQSource src[256]; > > + char *icutype; > > + uint32_t nr_irqs; > > + uint32_t *map; > > + uint32_t nr_sense; > > + uint32_t *init_sense; > > + > > + uint8_t ir[256]; > > + uint8_t dtcer[256]; > > + uint8_t ier[32]; > > + uint8_t ipr[142]; > > + uint8_t dmasr[4]; > > + uint16_t fir; > > + uint8_t nmisr; > > + uint8_t nmier; > > + uint8_t nmiclr; > > + uint8_t nmicr; > > + int req_irq; > > + qemu_irq _irq; > > + qemu_irq _fir; > > + qemu_irq _swi; > > +}; > > +typedef struct RXICUState RXICUState; > > + > > +#define TYPE_RXICU "rxicu" > > +#define RXICU(obj) OBJECT_CHECK(RXICUState, (obj), TYPE_RXICU) > > + > > +#define SWI 27 >=20 > enum { >=20 > > +#define TRG_LEVEL 0 > > +#define TRG_NEDGE 1 > > +#define TRG_PEDGE 2 > > +#define TRG_BEDGE 3 >=20 > }; >=20 > > + > > +#endif /* RX_ICU_H */ > > diff --git a/hw/intc/rx_icu.c b/hw/intc/rx_icu.c > > new file mode 100644 > > index 0000000000..345e047a45 > > --- /dev/null > > +++ b/hw/intc/rx_icu.c > > @@ -0,0 +1,375 @@ > > +/* > > + * RX Interrupt control unit >=20 > "Interrupt Control Unit" >=20 > "Warning: Only ICUa is supported." >=20 > > + * > > + * Datasheet: RX62N Group, RX621 Group User's Manual: Hardware > > + * (Rev.1.40 R01UH0033EJ0140) > > + * > > + * Copyright (c) 2019 Yoshinori Sato > > + * > > + * This program is free software; you can redistribute it and/or modif= y it > > + * under the terms and conditions of the GNU General Public License, > > + * version 2 or later, as published by the Free Software Foundation. > > + * > > + * This program is distributed in the hope it will be useful, but WITH= OUT > > + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY = or > > + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public Licen= se for > > + * more details. > > + * > > + * You should have received a copy of the GNU General Public License a= long with > > + * this program. If not, see . > > + */ > > + > > +#include "qemu/osdep.h" > > +#include "qemu-common.h" > > +#include "qemu/log.h" > > +#include "qapi/error.h" > > +#include "cpu.h" > > +#include "hw/hw.h" > > +#include "hw/sysbus.h" > > +#include "hw/registerfields.h" > > +#include "hw/intc/rx_icu.h" > > +#include "qemu/error-report.h" > > + > > +REG8(IR, 0) > > + FIELD(IR, IR, 0, 1) > > +REG8(DTCER, 0x100) > > + FIELD(DTCER, DTCE, 0, 1) > > +REG8(IER, 0x200) > > +REG8(SWINTR, 0x2e0) > > + FIELD(SWINTR, SWINT, 0, 1) > > +REG16(FIR, 0x2f0) > > + FIELD(FIR, FVCT, 0, 8) > > + FIELD(FIR, FIEN, 15, 1) > > +REG8(IPR, 0x300) > > + FIELD(IPR, IPR, 0, 4) > > +REG8(DMRSR, 0x400) > > +REG8(IRQCR, 0x500) > > + FIELD(IRQCR, IRQMD, 2, 2) > > +REG8(NMISR, 0x580) > > + FIELD(NMISR, NMIST, 0, 1) > > + FIELD(NMISR, LVDST, 1, 1) > > + FIELD(NMISR, OSTST, 2, 1) > > +REG8(NMIER, 0x581) > > + FIELD(NMIER, NMIEN, 0, 1) > > + FIELD(NMIER, LVDEN, 1, 1) > > + FIELD(NMIER, OSTEN, 2, 1) > > +REG8(NMICLR, 0x582) > > + FIELD(NMICLR, NMICLR, 0, 1) > > + FIELD(NMICLR, OSTCLR, 2, 1) > > +REG8(NMICR, 0x583) > > + FIELD(NMICR, NMIMD, 3, 1) > > + > > +#define request(icu, n) (icu->ipr[icu->map[n]] << 8 | n) > > + > > +static qemu_irq *rxicu_pin(RXICUState *icu, int n_IRQ) > > +{ > > + if ((icu->fir & R_FIR_FIEN_MASK) && > > + (icu->fir & R_FIR_FVCT_MASK) =3D=3D n_IRQ) { > > + return &icu->_fir; > > + } else { > > + return &icu->_irq; > > + } > > +} > > + > > +static void rxicu_request(RXICUState *icu, int n_IRQ) > > +{ > > + int enable; > > + > > + enable =3D icu->ier[n_IRQ / 8] & (1 << (n_IRQ & 7)); > > + if (n_IRQ > 0 && enable !=3D 0 && atomic_read(&icu->req_irq) < 0) { > > + atomic_set(&icu->req_irq, n_IRQ); > > + qemu_set_irq(*rxicu_pin(icu, n_IRQ), request(icu, n_IRQ)); > > + } > > +} > > + > > +static void rxicu_set_irq(void *opaque, int n_IRQ, int level) > > +{ > > + RXICUState *icu =3D opaque; > > + struct IRQSource *src; > > + int issue; > > + > > + if (n_IRQ >=3D 256) { >=20 > OK this should be RX_IRQ_COUNT (noted in later patch). >=20 > > + error_report("%s: IRQ %d out of range", __func__, n_IRQ); > > + return; > > + } > > + > > + src =3D &icu->src[n_IRQ]; > > + > > + level =3D (level !=3D 0); > > + switch (src->sense) { > > + case TRG_LEVEL: > > + /* level-sensitive irq */ > > + issue =3D level; > > + src->level =3D level; > > + break; > > + case TRG_NEDGE: > > + issue =3D (level =3D=3D 0 && src->level =3D=3D 1); > > + src->level =3D level; > > + break; > > + case TRG_PEDGE: > > + issue =3D (level =3D=3D 1 && src->level =3D=3D 0); > > + src->level =3D level; > > + break; > > + case TRG_BEDGE: > > + issue =3D ((level ^ src->level) & 1); > > + src->level =3D level; > > + break; > > + default: > > + g_assert_not_reached(); > > + } > > + if (issue =3D=3D 0 && src->sense =3D=3D TRG_LEVEL) { > > + icu->ir[n_IRQ] =3D 0; > > + if (atomic_read(&icu->req_irq) =3D=3D n_IRQ) { > > + /* clear request */ > > + qemu_set_irq(*rxicu_pin(icu, n_IRQ), 0); > > + atomic_set(&icu->req_irq, -1); > > + } > > + return; > > + } > > + if (issue) { > > + icu->ir[n_IRQ] =3D 1; > > + rxicu_request(icu, n_IRQ); > > + } > > +} > > + > > +static void rxicu_ack_irq(void *opaque, int no, int level) > > +{ > > + RXICUState *icu =3D opaque; > > + int i; > > + int n_IRQ; > > + int max_pri; > > + > > + n_IRQ =3D atomic_read(&icu->req_irq); > > + if (n_IRQ < 0) { > > + return; > > + } > > + atomic_set(&icu->req_irq, -1); > > + if (icu->src[n_IRQ].sense !=3D TRG_LEVEL) { > > + icu->ir[n_IRQ] =3D 0; > > + } > > + > > + max_pri =3D 0; > > + n_IRQ =3D -1; > > + for (i =3D 0; i < 256; i++) { > > + if (icu->ir[i]) { > > + if (max_pri < icu->ipr[icu->map[i]]) { > > + n_IRQ =3D i; > > + max_pri =3D icu->ipr[icu->map[i]]; > > + } > > + } > > + } > > + > > + if (n_IRQ >=3D 0) { > > + rxicu_request(icu, n_IRQ); > > + } > > +} > > + > > +static uint64_t icu_read(void *opaque, hwaddr addr, unsigned size) > > +{ > > + hwaddr offset =3D addr & 0xfff; >=20 > The region is 0x600 wide, why AND? (if required that would be & 0x5ff). >=20 > > + RXICUState *icu =3D opaque; > > + int reg =3D addr & 0xff; > > + > > + if ((offset !=3D A_FIR && size !=3D 1) || > > + (offset =3D=3D A_FIR && size !=3D 2)) { > > + qemu_log_mask(LOG_GUEST_ERROR, > > + "rx_icu: Invalid read size %08lx.\n", offset); > > + return 0xffffffffffffffffULL; >=20 > UINT64_MAX? >=20 > Here I get on 32bit host: >=20 > In file included from qemu/hw/intc/rx_icu.c:24:0: > qemu/hw/intc/rx_icu.c: In function 'icu_read': > qemu/hw/intc/rx_icu.c:176:23: error: format '%lx' expects argument of > type 'long unsigned int', but argument 2 has type 'hwaddr {aka long long > unsigned int}' [-Werror=3Dformat=3D] > "rx_icu: Invalid read size %08lx.\n", offset); > ^ > qemu/include/qemu/log.h:85:22: note: in definition of macro 'qemu_log_mas= k' > qemu_log(FMT, ## __VA_ARGS__); \ > ^ > qemu/hw/intc/rx_icu.c:208:23: error: format '%lx' expects argument of > type 'long unsigned int', but argument 2 has type 'hwaddr {aka long long > unsigned int}' [-Werror=3Dformat=3D] > "rx_icu: Register %08lx not implemented\n", offset= ); > ^ > qemu/include/qemu/log.h:85:22: note: in definition of macro 'qemu_log_mas= k' > qemu_log(FMT, ## __VA_ARGS__); \ > ^ > qemu/hw/intc/rx_icu.c: In function 'icu_write': > qemu/hw/intc/rx_icu.c:223:23: error: format '%lx' expects argument of > type 'long unsigned int', but argument 2 has type 'hwaddr {aka long long > unsigned int}' [-Werror=3Dformat=3D] > "rx_icu: Invalid write size at %08lx.\n", offset); > ^ > qemu/include/qemu/log.h:85:22: note: in definition of macro 'qemu_log_mas= k' > qemu_log(FMT, ## __VA_ARGS__); \ > ^ > qemu/hw/intc/rx_icu.c:276:23: error: format '%lx' expects argument of > type 'long unsigned int', but argument 2 has type 'hwaddr {aka long long > unsigned int}' [-Werror=3Dformat=3D] > "rx_icu: Register %08lx not implemented\n", offset= ); > ^ > qemu/include/qemu/log.h:85:22: note: in definition of macro 'qemu_log_mas= k' > qemu_log(FMT, ## __VA_ARGS__); \ > ^ > cc1: all warnings being treated as errors >=20 > Please fix using HWADDR_PRIX. >=20 > > + } > > + switch (offset) { > > + case A_IR ... A_IR + 0xff: > > + return icu->ir[reg] & R_IR_IR_MASK; > > + case A_DTCER ... A_DTCER + 0xff: > > + return icu->dtcer[reg] & R_DTCER_DTCE_MASK; > > + case A_IER ... A_IER + 0x1f: > > + return icu->ier[reg]; > > + case A_SWINTR: > > + return 0; > > + case A_FIR: > > + return icu->fir & (R_FIR_FIEN_MASK | R_FIR_FVCT_MASK); > > + case A_IPR ... A_IPR + 0x8f: > > + return icu->ipr[reg] & R_IPR_IPR_MASK; > > + case A_DMRSR: > > + case A_DMRSR + 4: > > + case A_DMRSR + 8: > > + case A_DMRSR + 12: > > + return icu->dmasr[reg >> 2]; > > + case A_IRQCR ... A_IRQCR + 0x1f: > > + return icu->src[64 + reg].sense << R_IRQCR_IRQMD_SHIFT; > > + case A_NMISR: > > + case A_NMICLR: > > + return 0; > > + case A_NMIER: > > + return icu->nmier; > > + case A_NMICR: > > + return icu->nmicr; > > + default: > > + qemu_log_mask(LOG_UNIMP, > > + "rx_icu: Register %08lx not implemented\n", offs= et); > > + break; > > + } > > + return 0xffffffffffffffffULL; >=20 > UINT64_MAX >=20 > > +} > > + > > +static void icu_write(void *opaque, hwaddr addr, uint64_t val, unsigne= d size) > > +{ > > + hwaddr offset =3D addr & 0xfff; >=20 > AND not needed IMO. >=20 > > + RXICUState *icu =3D opaque; > > + int reg =3D addr & 0xff; > > + > > + if ((offset !=3D A_FIR && size !=3D 1) || > > + (offset =3D=3D A_FIR && size !=3D 2)) { > > + qemu_log_mask(LOG_GUEST_ERROR, > > + "rx_icu: Invalid write size at %08lx.\n", offset= ); >=20 > Oh, I think we don't end logging with trailing dot... >=20 > > + return; > > + } > > + switch (offset) { > > + case A_IR ... A_IR + 0xff: > > + if (icu->src[reg].sense !=3D TRG_LEVEL && val =3D=3D 0) { > > + icu->ir[reg] =3D 0; > > + } > > + break; > > + case A_DTCER ... A_DTCER + 0xff: > > + icu->dtcer[reg] =3D val & R_DTCER_DTCE_MASK; > > + qemu_log_mask(LOG_UNIMP, > > + "rx_icu: DTC not implemented\n"); > > + break; > > + case A_IER ... A_IER + 0x1f: > > + icu->ier[reg] =3D val; > > + break; > > + case A_SWINTR: > > + if (val & R_SWINTR_SWINT_MASK) { > > + qemu_irq_pulse(icu->_swi); > > + } > > + break; > > + case A_FIR: > > + icu->fir =3D val & (R_FIR_FIEN_MASK | R_FIR_FVCT_MASK); > > + break; > > + case A_IPR ... A_IPR + 0x8f: > > + icu->ipr[reg] =3D val & R_IPR_IPR_MASK; > > + break; > > + case A_DMRSR: > > + case A_DMRSR + 4: > > + case A_DMRSR + 8: > > + case A_DMRSR + 12: > > + icu->dmasr[reg >> 2] =3D val; > > + qemu_log_mask(LOG_UNIMP, > > + "rx_icu: DMAC not implemented\n"); > > + break; > > + case A_IRQCR ... A_IRQCR + 0x1f: > > + icu->src[64 + reg].sense =3D val >> R_IRQCR_IRQMD_SHIFT; > > + break; > > + case A_NMICLR: > > + break; > > + case A_NMIER: > > + icu->nmier |=3D val & (R_NMIER_NMIEN_MASK | > > + R_NMIER_LVDEN_MASK | > > + R_NMIER_OSTEN_MASK); > > + break; > > + case A_NMICR: > > + if ((icu->nmier & R_NMIER_NMIEN_MASK) =3D=3D 0) { > > + icu->nmicr =3D val & R_NMICR_NMIMD_MASK; > > + } > > + break; > > + default: > > + qemu_log_mask(LOG_UNIMP, > > + "rx_icu: Register %08lx not implemented\n", offs= et); > > + break; > > + } > > +} > > + > > +static const MemoryRegionOps icu_ops =3D { > > + .write =3D icu_write, > > + .read =3D icu_read, > > + .endianness =3D DEVICE_LITTLE_ENDIAN, > > + .impl =3D { > > + .max_access_size =3D 2, > > + }, > > +}; > > + > > +static void rxicu_realize(DeviceState *dev, Error **errp) > > +{ > > + RXICUState *icu =3D RXICU(dev); > > + int i, j; > > + > > + if (icu->init_sense =3D=3D NULL) { > > + qemu_log_mask(LOG_GUEST_ERROR, > > + "rx_icu: trigger-level property must be set."); > > + return; > > + } > > + for (i =3D j =3D 0; i < 256; i++) { >=20 > RX_IRQ_COUNT >=20 > > + if (icu->init_sense[j] =3D=3D i) { > > + icu->src[i].sense =3D TRG_LEVEL; > > + if (j < icu->nr_sense) { > > + j++; > > + } > > + } else > > + icu->src[i].sense =3D TRG_PEDGE; > > + } > > + icu->req_irq =3D -1; > > +} > > + > > +static void rxicu_init(Object *obj) > > +{ > > + SysBusDevice *d =3D SYS_BUS_DEVICE(obj); > > + RXICUState *icu =3D RXICU(obj); > > + > > + memory_region_init_io(&icu->memory, OBJECT(icu), &icu_ops, > > + icu, "rx-icu", 0x600); > > + sysbus_init_mmio(d, &icu->memory); > > + > > + qdev_init_gpio_in(DEVICE(d), rxicu_set_irq, 256); >=20 > RX_IRQ_COUNT >=20 > > + qdev_init_gpio_in_named(DEVICE(d), rxicu_ack_irq, "ack", 1); > > + sysbus_init_irq(d, &icu->_irq); > > + sysbus_init_irq(d, &icu->_fir); > > + sysbus_init_irq(d, &icu->_swi); > > +} > > + > > +static void rxicu_fini(Object *obj) > > +{ > > + RXICUState *icu =3D RXICU(obj); > > + g_free(icu->map); > > + g_free(icu->init_sense); > > +} > > + > > +static const VMStateDescription vmstate_rxicu =3D { > > + .name =3D "rx-icu", > > + .version_id =3D 1, > > + .minimum_version_id =3D 1, > > + .fields =3D (VMStateField[]) { > > + VMSTATE_END_OF_LIST() > > + } > > +}; > > + > > +static Property rxicu_properties[] =3D { > > + DEFINE_PROP_ARRAY("ipr-map", RXICUState, nr_irqs, map, > > + qdev_prop_uint32, uint32_t), > > + DEFINE_PROP_ARRAY("trigger-level", RXICUState, nr_sense, init_sens= e, > > + qdev_prop_uint32, uint32_t), > > + DEFINE_PROP_END_OF_LIST(), > > +}; > > + > > +static void rxicu_class_init(ObjectClass *klass, void *data) > > +{ > > + DeviceClass *dc =3D DEVICE_CLASS(klass); > > + > > + dc->realize =3D rxicu_realize; > > + dc->props =3D rxicu_properties; > > + dc->vmsd =3D &vmstate_rxicu; > > +} > > + > > +static const TypeInfo rxicu_info =3D { > > + .name =3D TYPE_RXICU, > > + .parent =3D TYPE_SYS_BUS_DEVICE, > > + .instance_size =3D sizeof(RXICUState), > > + .instance_init =3D rxicu_init, > > + .instance_finalize =3D rxicu_fini, > > + .class_init =3D rxicu_class_init, > > +}; > > + > > +static void rxicu_register_types(void) > > +{ > > + type_register_static(&rxicu_info); > > +} > > + > > +type_init(rxicu_register_types) > > diff --git a/hw/intc/Makefile.objs b/hw/intc/Makefile.objs > > index df712c3e6c..b54b09b12e 100644 > > --- a/hw/intc/Makefile.objs > > +++ b/hw/intc/Makefile.objs > > @@ -48,3 +48,4 @@ obj-$(CONFIG_ARM_GIC) +=3D arm_gicv3_cpuif.o > > obj-$(CONFIG_MIPS_CPS) +=3D mips_gic.o > > obj-$(CONFIG_NIOS2) +=3D nios2_iic.o > > obj-$(CONFIG_OMPIC) +=3D ompic.o > > +obj-$(CONFIG_RX) +=3D rx_icu.o >=20 > Why not declare a RENESAS_ICU in Kconfig and use it? ICU only using RX. Timer and SCI using other Renesas MCUs. So ICU have RX specific name. > obj-$(CONFIG_RENESAS_ICU) +=3D rx_icu.o >=20 > Good work! >=20 > Tested-by: Philippe Mathieu-Daud=E9 >=20 --=20 Yosinori Sato