diff for duplicates of <87egew98ty.fsf@free-electrons.com> diff --git a/a/1.txt b/N1/1.txt index c95ea44..db6a8a8 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -1,6 +1,6 @@ Hi Russell, - On dim., d?c. 06 2015, Russell King <rmk+kernel@arm.linux.org.uk> wrote: + On dim., déc. 06 2015, Russell King <rmk+kernel-lFZ/pmaqli7XmaaqVzeoHQ@public.gmane.org> wrote: > Add support for the SolidRun Armada 388 Clearfog A1 board. This board > has an Armada 388 microsom, dedicated gigabit ethernet, six switched @@ -10,7 +10,7 @@ Hi Russell, > This DT file adds support for all board facilities with the exception > of full SFP support. > -> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> +> Signed-off-by: Russell King <rmk+kernel-lFZ/pmaqli7XmaaqVzeoHQ@public.gmane.org> I made some tests it on the Clearfog v2.0 I have: Ethernet (CON8 and J11), i2c (using i2cdetect), USB stick on CON7. @@ -20,7 +20,7 @@ the High Speed profile and not the Super Speed one. But I think it is because of the Serdes configuration done in U-Boot. -so Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com> +so Acked-by: Gregory CLEMENT <gregory.clement-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org> and applied on mvebu/dt. Thanks, @@ -133,7 +133,7 @@ Gregory > + > + soc { > + internal-regs { -> + ethernet at 30000 { +> + ethernet@30000 { > + phy-mode = "sgmii"; > + status = "okay"; > + @@ -143,7 +143,7 @@ Gregory > + }; > + }; > + -> + ethernet at 34000 { +> + ethernet@34000 { > + phy-mode = "sgmii"; > + status = "okay"; > + @@ -153,7 +153,7 @@ Gregory > + }; > + }; > + -> + i2c at 11000 { +> + i2c@11000 { > + /* Is there anything on this? */ > + clock-frequency = <100000>; > + pinctrl-0 = <&i2c0_pins>; @@ -179,7 +179,7 @@ Gregory > + * 14-SFP_TX_DISABLE > + * 15-SFP_MOD_DEF0 > + */ -> + expander0: gpio-expander at 20 { +> + expander0: gpio-expander@20 { > + /* > + * This is how it should be: > + * compatible = "onnn,pca9655", @@ -265,7 +265,7 @@ Gregory > + }; > + > + /* The MCP3021 is 100kHz clock only */ -> + mikrobus_adc: mcp3021 at 4c { +> + mikrobus_adc: mcp3021@4c { > + compatible = "microchip,mcp3021"; > + reg = <0x4c>; > + }; @@ -273,7 +273,7 @@ Gregory > + /* Also something at 0x64 */ > + }; > + -> + i2c at 11100 { +> + i2c@11100 { > + /* > + * Routed to SFP, mikrobus, and PCIe. > + * SFP limits this to 100kHz, and requires @@ -290,11 +290,11 @@ Gregory > + status = "okay"; > + }; > + -> + mdio at 72004 { +> + mdio@72004 { > + pinctrl-0 = <&mdio_pins>; > + pinctrl-names = "default"; > + -> + phy_dedicated: ethernet-phy at 0 { +> + phy_dedicated: ethernet-phy@0 { > + /* > + * Annoyingly, the marvell phy driver > + * configures the LED register, rather @@ -306,7 +306,7 @@ Gregory > + }; > + }; > + -> + pinctrl at 18000 { +> + pinctrl@18000 { > + clearfog_dsa0_clk_pins: clearfog-dsa0-clk-pins { > + marvell,pins = "mpp46"; > + marvell,function = "ref"; @@ -353,17 +353,17 @@ Gregory > + }; > + }; > + -> + sata at a8000 { +> + sata@a8000 { > + /* pinctrl? */ > + status = "okay"; > + }; > + -> + sata at e0000 { +> + sata@e0000 { > + /* pinctrl? */ > + status = "okay"; > + }; > + -> + sdhci at d8000 { +> + sdhci@d8000 { > + bus-width = <4>; > + cd-gpios = <&gpio0 20 GPIO_ACTIVE_LOW>; > + no-1-8-v; @@ -375,14 +375,14 @@ Gregory > + wp-inverted; > + }; > + -> + serial at 12100 { +> + serial@12100 { > + /* mikrobus uart */ > + pinctrl-0 = <&mikro_uart_pins>; > + pinctrl-names = "default"; > + status = "okay"; > + }; > + -> + spi at 10680 { +> + spi@10680 { > + /* > + * We don't seem to have the W25Q32 on the > + * A1 Rev 2.0 boards, so disable SPI. @@ -396,7 +396,7 @@ Gregory > + pinctrl-names = "default"; > + status = "okay"; > + -> + spi-flash at 0 { +> + spi-flash@0 { > + #address-cells = <1>; > + #size-cells = <0>; > + compatible = "w25q32", "jedec,spi-nor"; @@ -406,17 +406,17 @@ Gregory > + }; > + }; > + -> + usb at 58000 { +> + usb@58000 { > + /* CON3, nearest power. */ > + status = "okay"; > + }; > + -> + usb3 at f0000 { +> + usb3@f0000 { > + /* CON2, nearest CPU, USB2 only. */ > + status = "okay"; > + }; > + -> + usb3 at f8000 { +> + usb3@f8000 { > + /* CON7 */ > + status = "okay"; > + }; @@ -428,12 +428,12 @@ Gregory > + * The two PCIe units are accessible through > + * the mini-PCIe connectors on the board. > + */ -> + pcie at 2,0 { +> + pcie@2,0 { > + /* Port 1, Lane 0. CON3, nearest power. */ > + reset-gpios = <&expander0 1 GPIO_ACTIVE_LOW>; > + status = "okay"; > + }; -> + pcie at 3,0 { +> + pcie@3,0 { > + /* Port 2, Lane 0. CON2, nearest CPU. */ > + reset-gpios = <&expander0 2 GPIO_ACTIVE_LOW>; > + status = "okay"; @@ -441,7 +441,7 @@ Gregory > + }; > + }; > + -> + dsa at 0 { +> + dsa@0 { > + compatible = "marvell,dsa"; > + dsa,ethernet = <ð1>; > + dsa,mii-bus = <&mdio>; @@ -450,42 +450,42 @@ Gregory > + #address-cells = <2>; > + #size-cells = <0>; > + -> + switch at 0 { +> + switch@0 { > + #address-cells = <1>; > + #size-cells = <0>; > + reg = <4 0>; > + -> + port at 0 { +> + port@0 { > + reg = <0>; > + label = "lan1"; > + }; > + -> + port at 1 { +> + port@1 { > + reg = <1>; > + label = "lan2"; > + }; > + -> + port at 2 { +> + port@2 { > + reg = <2>; > + label = "lan3"; > + }; > + -> + port at 3 { +> + port@3 { > + reg = <3>; > + label = "lan4"; > + }; > + -> + port at 4 { +> + port@4 { > + reg = <4>; > + label = "lan5"; > + }; > + -> + port at 5 { +> + port@5 { > + reg = <5>; > + label = "cpu"; > + }; > + -> + port at 6 { +> + port@6 { > + /* 88E1512 external phy */ > + reg = <6>; > + label = "lan6"; @@ -580,7 +580,7 @@ Gregory > + MBUS_ID(0x09, 0x15) 0 0xf1110000 0x10000>; > + > + internal-regs { -> + ethernet at 70000 { +> + ethernet@70000 { > + pinctrl-0 = <&ge0_rgmii_pins>; > + pinctrl-names = "default"; > + phy = <&phy_dedicated>; @@ -588,7 +588,7 @@ Gregory > + status = "okay"; > + }; > + -> + mdio at 72004 { +> + mdio@72004 { > + /* > + * Add the phy clock here, so the phy can be > + * accessed to read its IDs prior to binding @@ -597,7 +597,7 @@ Gregory > + pinctrl-0 = <&mdio_pins µsom_phy_clk_pins>; > + pinctrl-names = "default"; > + -> + phy_dedicated: ethernet-phy at 0 { +> + phy_dedicated: ethernet-phy@0 { > + /* > + * Annoyingly, the marvell phy driver > + * configures the LED register, rather @@ -609,14 +609,14 @@ Gregory > + }; > + }; > + -> + pinctrl at 18000 { +> + pinctrl@18000 { > + microsom_phy_clk_pins: microsom-phy-clk-pins { > + marvell,pins = "mpp45"; > + marvell,function = "ref"; > + }; > + }; > + -> + rtc at a3800 { +> + rtc@a3800 { > + /* > + * If the rtc doesn't work, run "date reset" > + * twice in u-boot. @@ -624,7 +624,7 @@ Gregory > + status = "okay"; > + }; > + -> + serial at 12000 { +> + serial@12000 { > + pinctrl-0 = <&uart0_pins>; > + pinctrl-names = "default"; > + status = "okay"; @@ -641,3 +641,7 @@ Gregory Clement, Free Electrons Kernel, drivers, real-time and embedded Linux development, consulting, training and support. http://free-electrons.com +-- +To unsubscribe from this list: send the line "unsubscribe devicetree" in +the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org +More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/a/content_digest b/N1/content_digest index 15d1bc1..d43628c 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -1,13 +1,24 @@ "ref\0E1a5hDy-0002rC-Oe@rmk-PC.arm.linux.org.uk\0" - "From\0gregory.clement@free-electrons.com (Gregory CLEMENT)\0" - "Subject\0[PATCH v2] ARM: dts: Add SolidRun Armada 388 Clearfog A1 DT file\0" + "ref\0E1a5hDy-0002rC-Oe-eh5Bv4kxaXIANfyc6IWni62ZND6+EDdj@public.gmane.org\0" + "From\0Gregory CLEMENT <gregory.clement-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>\0" + "Subject\0Re: [PATCH v2] ARM: dts: Add SolidRun Armada 388 Clearfog A1 DT file\0" "Date\0Tue, 08 Dec 2015 17:57:45 +0100\0" - "To\0linux-arm-kernel@lists.infradead.org\0" + "To\0Russell King <rmk+kernel-lFZ/pmaqli7XmaaqVzeoHQ@public.gmane.org>\0" + "Cc\0Jason Cooper <jason-NLaQJdtUoK4Be96aLqz0jA@public.gmane.org>" + Andrew Lunn <andrew-g2DYL2Zd6BY@public.gmane.org> + Rob Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org> + Pawel Moll <pawel.moll-5wv7dgnIgG8@public.gmane.org> + Mark Rutland <mark.rutland-5wv7dgnIgG8@public.gmane.org> + Ian Campbell <ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg@public.gmane.org> + Kumar Gala <galak-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org> + Sebastian Hesselbarth <sebastian.hesselbarth-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> + devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org + " linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org\0" "\00:1\0" "b\0" "Hi Russell,\n" " \n" - " On dim., d?c. 06 2015, Russell King <rmk+kernel@arm.linux.org.uk> wrote:\n" + " On dim., d\303\251c. 06 2015, Russell King <rmk+kernel-lFZ/pmaqli7XmaaqVzeoHQ@public.gmane.org> wrote:\n" "\n" "> Add support for the SolidRun Armada 388 Clearfog A1 board. This board\n" "> has an Armada 388 microsom, dedicated gigabit ethernet, six switched\n" @@ -17,7 +28,7 @@ "> This DT file adds support for all board facilities with the exception\n" "> of full SFP support.\n" ">\n" - "> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>\n" + "> Signed-off-by: Russell King <rmk+kernel-lFZ/pmaqli7XmaaqVzeoHQ@public.gmane.org>\n" "\n" "I made some tests it on the Clearfog v2.0 I have: Ethernet (CON8 and\n" "J11), i2c (using i2cdetect), USB stick on CON7.\n" @@ -27,7 +38,7 @@ "because of the Serdes configuration done in U-Boot.\n" "\n" "\n" - "so Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com>\n" + "so Acked-by: Gregory CLEMENT <gregory.clement-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>\n" "and applied on mvebu/dt.\n" "\n" "Thanks,\n" @@ -140,7 +151,7 @@ "> +\n" "> +\tsoc {\n" "> +\t\tinternal-regs {\n" - "> +\t\t\tethernet at 30000 {\n" + "> +\t\t\tethernet@30000 {\n" "> +\t\t\t\tphy-mode = \"sgmii\";\n" "> +\t\t\t\tstatus = \"okay\";\n" "> +\n" @@ -150,7 +161,7 @@ "> +\t\t\t\t};\n" "> +\t\t\t};\n" "> +\n" - "> +\t\t\tethernet at 34000 {\n" + "> +\t\t\tethernet@34000 {\n" "> +\t\t\t\tphy-mode = \"sgmii\";\n" "> +\t\t\t\tstatus = \"okay\";\n" "> +\n" @@ -160,7 +171,7 @@ "> +\t\t\t\t};\n" "> +\t\t\t};\n" "> +\n" - "> +\t\t\ti2c at 11000 {\n" + "> +\t\t\ti2c@11000 {\n" "> +\t\t\t\t/* Is there anything on this? */\n" "> +\t\t\t\tclock-frequency = <100000>;\n" "> +\t\t\t\tpinctrl-0 = <&i2c0_pins>;\n" @@ -186,7 +197,7 @@ "> +\t\t\t\t * 14-SFP_TX_DISABLE\n" "> +\t\t\t\t * 15-SFP_MOD_DEF0\n" "> +\t\t\t\t */\n" - "> +\t\t\t\texpander0: gpio-expander at 20 {\n" + "> +\t\t\t\texpander0: gpio-expander@20 {\n" "> +\t\t\t\t\t/*\n" "> +\t\t\t\t\t * This is how it should be:\n" "> +\t\t\t\t\t * compatible = \"onnn,pca9655\",\n" @@ -272,7 +283,7 @@ "> +\t\t\t\t};\n" "> +\n" "> +\t\t\t\t/* The MCP3021 is 100kHz clock only */\n" - "> +\t\t\t\tmikrobus_adc: mcp3021 at 4c {\n" + "> +\t\t\t\tmikrobus_adc: mcp3021@4c {\n" "> +\t\t\t\t\tcompatible = \"microchip,mcp3021\";\n" "> +\t\t\t\t\treg = <0x4c>;\n" "> +\t\t\t\t};\n" @@ -280,7 +291,7 @@ "> +\t\t\t\t/* Also something at 0x64 */\n" "> +\t\t\t};\n" "> +\n" - "> +\t\t\ti2c at 11100 {\n" + "> +\t\t\ti2c@11100 {\n" "> +\t\t\t\t/*\n" "> +\t\t\t\t * Routed to SFP, mikrobus, and PCIe.\n" "> +\t\t\t\t * SFP limits this to 100kHz, and requires\n" @@ -297,11 +308,11 @@ "> +\t\t\t\tstatus = \"okay\";\n" "> +\t\t\t};\n" "> +\n" - "> +\t\t\tmdio at 72004 {\n" + "> +\t\t\tmdio@72004 {\n" "> +\t\t\t\tpinctrl-0 = <&mdio_pins>;\n" "> +\t\t\t\tpinctrl-names = \"default\";\n" "> +\n" - "> +\t\t\t\tphy_dedicated: ethernet-phy at 0 {\n" + "> +\t\t\t\tphy_dedicated: ethernet-phy@0 {\n" "> +\t\t\t\t\t/*\n" "> +\t\t\t\t\t * Annoyingly, the marvell phy driver\n" "> +\t\t\t\t\t * configures the LED register, rather\n" @@ -313,7 +324,7 @@ "> +\t\t\t\t};\n" "> +\t\t\t};\n" "> +\n" - "> +\t\t\tpinctrl at 18000 {\n" + "> +\t\t\tpinctrl@18000 {\n" "> +\t\t\t\tclearfog_dsa0_clk_pins: clearfog-dsa0-clk-pins {\n" "> +\t\t\t\t\tmarvell,pins = \"mpp46\";\n" "> +\t\t\t\t\tmarvell,function = \"ref\";\n" @@ -360,17 +371,17 @@ "> +\t\t\t\t};\n" "> +\t\t\t};\n" "> +\n" - "> +\t\t\tsata at a8000 {\n" + "> +\t\t\tsata@a8000 {\n" "> +\t\t\t\t/* pinctrl? */\n" "> +\t\t\t\tstatus = \"okay\";\n" "> +\t\t\t};\n" "> +\n" - "> +\t\t\tsata at e0000 {\n" + "> +\t\t\tsata@e0000 {\n" "> +\t\t\t\t/* pinctrl? */\n" "> +\t\t\t\tstatus = \"okay\";\n" "> +\t\t\t};\n" "> +\n" - "> +\t\t\tsdhci at d8000 {\n" + "> +\t\t\tsdhci@d8000 {\n" "> +\t\t\t\tbus-width = <4>;\n" "> +\t\t\t\tcd-gpios = <&gpio0 20 GPIO_ACTIVE_LOW>;\n" "> +\t\t\t\tno-1-8-v;\n" @@ -382,14 +393,14 @@ "> +\t\t\t\twp-inverted;\n" "> +\t\t\t};\n" "> +\n" - "> +\t\t\tserial at 12100 {\n" + "> +\t\t\tserial@12100 {\n" "> +\t\t\t\t/* mikrobus uart */\n" "> +\t\t\t\tpinctrl-0 = <&mikro_uart_pins>;\n" "> +\t\t\t\tpinctrl-names = \"default\";\n" "> +\t\t\t\tstatus = \"okay\";\n" "> +\t\t\t};\n" "> +\n" - "> +\t\t\tspi at 10680 {\n" + "> +\t\t\tspi@10680 {\n" "> +\t\t\t\t/*\n" "> +\t\t\t\t * We don't seem to have the W25Q32 on the\n" "> +\t\t\t\t * A1 Rev 2.0 boards, so disable SPI.\n" @@ -403,7 +414,7 @@ "> +\t\t\t\tpinctrl-names = \"default\";\n" "> +\t\t\t\tstatus = \"okay\";\n" "> +\n" - "> +\t\t\t\tspi-flash at 0 {\n" + "> +\t\t\t\tspi-flash@0 {\n" "> +\t\t\t\t\t#address-cells = <1>;\n" "> +\t\t\t\t\t#size-cells = <0>;\n" "> +\t\t\t\t\tcompatible = \"w25q32\", \"jedec,spi-nor\";\n" @@ -413,17 +424,17 @@ "> +\t\t\t\t};\n" "> +\t\t\t};\n" "> +\n" - "> +\t\t\tusb at 58000 {\n" + "> +\t\t\tusb@58000 {\n" "> +\t\t\t\t/* CON3, nearest power. */\n" "> +\t\t\t\tstatus = \"okay\";\n" "> +\t\t\t};\n" "> +\n" - "> +\t\t\tusb3 at f0000 {\n" + "> +\t\t\tusb3@f0000 {\n" "> +\t\t\t\t/* CON2, nearest CPU, USB2 only. */\n" "> +\t\t\t\tstatus = \"okay\";\n" "> +\t\t\t};\n" "> +\n" - "> +\t\t\tusb3 at f8000 {\n" + "> +\t\t\tusb3@f8000 {\n" "> +\t\t\t\t/* CON7 */\n" "> +\t\t\t\tstatus = \"okay\";\n" "> +\t\t\t};\n" @@ -435,12 +446,12 @@ "> +\t\t\t * The two PCIe units are accessible through\n" "> +\t\t\t * the mini-PCIe connectors on the board.\n" "> +\t\t\t */\n" - "> +\t\t\tpcie at 2,0 {\n" + "> +\t\t\tpcie@2,0 {\n" "> +\t\t\t\t/* Port 1, Lane 0. CON3, nearest power. */\n" "> +\t\t\t\treset-gpios = <&expander0 1 GPIO_ACTIVE_LOW>;\n" "> +\t\t\t\tstatus = \"okay\";\n" "> +\t\t\t};\n" - "> +\t\t\tpcie at 3,0 {\n" + "> +\t\t\tpcie@3,0 {\n" "> +\t\t\t\t/* Port 2, Lane 0. CON2, nearest CPU. */\n" "> +\t\t\t\treset-gpios = <&expander0 2 GPIO_ACTIVE_LOW>;\n" "> +\t\t\t\tstatus = \"okay\";\n" @@ -448,7 +459,7 @@ "> +\t\t};\n" "> +\t};\n" "> +\n" - "> +\tdsa at 0 {\n" + "> +\tdsa@0 {\n" "> +\t\tcompatible = \"marvell,dsa\";\n" "> +\t\tdsa,ethernet = <ð1>;\n" "> +\t\tdsa,mii-bus = <&mdio>;\n" @@ -457,42 +468,42 @@ "> +\t\t#address-cells = <2>;\n" "> +\t\t#size-cells = <0>;\n" "> +\n" - "> +\t\tswitch at 0 {\n" + "> +\t\tswitch@0 {\n" "> +\t\t\t#address-cells = <1>;\n" "> +\t\t\t#size-cells = <0>;\n" "> +\t\t\treg = <4 0>;\n" "> +\n" - "> +\t\t\tport at 0 {\n" + "> +\t\t\tport@0 {\n" "> +\t\t\t\treg = <0>;\n" "> +\t\t\t\tlabel = \"lan1\";\n" "> +\t\t\t};\n" "> +\n" - "> +\t\t\tport at 1 {\n" + "> +\t\t\tport@1 {\n" "> +\t\t\t\treg = <1>;\n" "> +\t\t\t\tlabel = \"lan2\";\n" "> +\t\t\t};\n" "> +\n" - "> +\t\t\tport at 2 {\n" + "> +\t\t\tport@2 {\n" "> +\t\t\t\treg = <2>;\n" "> +\t\t\t\tlabel = \"lan3\";\n" "> +\t\t\t};\n" "> +\n" - "> +\t\t\tport at 3 {\n" + "> +\t\t\tport@3 {\n" "> +\t\t\t\treg = <3>;\n" "> +\t\t\t\tlabel = \"lan4\";\n" "> +\t\t\t};\n" "> +\n" - "> +\t\t\tport at 4 {\n" + "> +\t\t\tport@4 {\n" "> +\t\t\t\treg = <4>;\n" "> +\t\t\t\tlabel = \"lan5\";\n" "> +\t\t\t};\n" "> +\n" - "> +\t\t\tport at 5 {\n" + "> +\t\t\tport@5 {\n" "> +\t\t\t\treg = <5>;\n" "> +\t\t\t\tlabel = \"cpu\";\n" "> +\t\t\t};\n" "> +\n" - "> +\t\t\tport at 6 {\n" + "> +\t\t\tport@6 {\n" "> +\t\t\t\t/* 88E1512 external phy */\n" "> +\t\t\t\treg = <6>;\n" "> +\t\t\t\tlabel = \"lan6\";\n" @@ -587,7 +598,7 @@ "> +\t\t\t MBUS_ID(0x09, 0x15) 0 0xf1110000 0x10000>;\n" "> +\n" "> +\t\tinternal-regs {\n" - "> +\t\t\tethernet at 70000 {\n" + "> +\t\t\tethernet@70000 {\n" "> +\t\t\t\tpinctrl-0 = <&ge0_rgmii_pins>;\n" "> +\t\t\t\tpinctrl-names = \"default\";\n" "> +\t\t\t\tphy = <&phy_dedicated>;\n" @@ -595,7 +606,7 @@ "> +\t\t\t\tstatus = \"okay\";\n" "> +\t\t\t};\n" "> +\n" - "> +\t\t\tmdio at 72004 {\n" + "> +\t\t\tmdio@72004 {\n" "> +\t\t\t\t/*\n" "> +\t\t\t\t * Add the phy clock here, so the phy can be\n" "> +\t\t\t\t * accessed to read its IDs prior to binding\n" @@ -604,7 +615,7 @@ "> +\t\t\t\tpinctrl-0 = <&mdio_pins µsom_phy_clk_pins>;\n" "> +\t\t\t\tpinctrl-names = \"default\";\n" "> +\n" - "> +\t\t\t\tphy_dedicated: ethernet-phy at 0 {\n" + "> +\t\t\t\tphy_dedicated: ethernet-phy@0 {\n" "> +\t\t\t\t\t/*\n" "> +\t\t\t\t\t * Annoyingly, the marvell phy driver\n" "> +\t\t\t\t\t * configures the LED register, rather\n" @@ -616,14 +627,14 @@ "> +\t\t\t\t};\n" "> +\t\t\t};\n" "> +\n" - "> +\t\t\tpinctrl at 18000 {\n" + "> +\t\t\tpinctrl@18000 {\n" "> +\t\t\t\tmicrosom_phy_clk_pins: microsom-phy-clk-pins {\n" "> +\t\t\t\t\tmarvell,pins = \"mpp45\";\n" "> +\t\t\t\t\tmarvell,function = \"ref\";\n" "> +\t\t\t\t};\n" "> +\t\t\t};\n" "> +\n" - "> +\t\t\trtc at a3800 {\n" + "> +\t\t\trtc@a3800 {\n" "> +\t\t\t\t/*\n" "> +\t\t\t\t * If the rtc doesn't work, run \"date reset\"\n" "> +\t\t\t\t * twice in u-boot.\n" @@ -631,7 +642,7 @@ "> +\t\t\t\tstatus = \"okay\";\n" "> +\t\t\t};\n" "> +\n" - "> +\t\t\tserial at 12000 {\n" + "> +\t\t\tserial@12000 {\n" "> +\t\t\t\tpinctrl-0 = <&uart0_pins>;\n" "> +\t\t\t\tpinctrl-names = \"default\";\n" "> +\t\t\t\tstatus = \"okay\";\n" @@ -647,6 +658,10 @@ "Gregory Clement, Free Electrons\n" "Kernel, drivers, real-time and embedded Linux\n" "development, consulting, training and support.\n" - http://free-electrons.com + "http://free-electrons.com\n" + "--\n" + "To unsubscribe from this list: send the line \"unsubscribe devicetree\" in\n" + "the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org\n" + More majordomo info at http://vger.kernel.org/majordomo-info.html -6cd0131663602d5d47548ca4562e7beb6b8ca9cc64e202144d791fe138ecd1ca +c64c9509879cdcf20dedcbb4f82ecc5e690ecfb43627d5065fdda8075930f4b9
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