From mboxrd@z Thu Jan 1 00:00:00 1970 From: Kevin Hilman Subject: Re: oprofile and ARM A9 hardware counter Date: Tue, 03 Apr 2012 16:14:19 -0700 Message-ID: <87ehs4pfw4.fsf@ti.com> References: <20120403092524.GD17741@mudshark.cambridge.arm.com> <20120403094749.GH17741@mudshark.cambridge.arm.com> <20120403123444.GL17741@mudshark.cambridge.arm.com> <878vicsxef.fsf@ti.com> <20120403160706.GP17741@mudshark.cambridge.arm.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Return-path: Received: from na3sys009aog116.obsmtp.com ([74.125.149.240]:56316 "EHLO na3sys009aog116.obsmtp.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754860Ab2DCXOV (ORCPT ); Tue, 3 Apr 2012 19:14:21 -0400 Received: by pbcwz17 with SMTP id wz17so391486pbc.41 for ; Tue, 03 Apr 2012 16:14:20 -0700 (PDT) In-Reply-To: <20120403160706.GP17741@mudshark.cambridge.arm.com> (Will Deacon's message of "Tue, 3 Apr 2012 17:07:06 +0100") Sender: linux-omap-owner@vger.kernel.org List-Id: linux-omap@vger.kernel.org To: Will Deacon Cc: "Shilimkar, Santosh" , Ming Lei , "eranian@gmail.com" , Maynard Johnson , Lik Lik , "oprofile-list@lists.sourceforge.net" , "linux-omap@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , Paul Walmsley , Benoit Cousson Will Deacon writes: [...] > Right. Can you confirm whether the PMU/CTI interrupts fire for you please? > Just run perf top and look at /proc/interrupts while it's running. You > should see a couple of arm-pmu entries in there and hopefully numbers > 0. Ah, I see now (I'm a perf newbie.) Indeed, like you, I have to change the EMU clock domain to SWSUP[1] in order to see any interrupts and see anything in perf top. This isn't really a mergeable workaround, so I'll look into this a little closer with Santosh to see what we can do once we fully understand the HW problem. Kevin [1] diff --git a/arch/arm/mach-omap2/clockdomains44xx_data.c b/arch/arm/mach-omap2/clockdomains44xx_data.c index 9299ac2..41d2260 100644 --- a/arch/arm/mach-omap2/clockdomains44xx_data.c +++ b/arch/arm/mach-omap2/clockdomains44xx_data.c @@ -390,7 +390,7 @@ static struct clockdomain emu_sys_44xx_clkdm = { .prcm_partition = OMAP4430_PRM_PARTITION, .cm_inst = OMAP4430_PRM_EMU_CM_INST, .clkdm_offs = OMAP4430_PRM_EMU_CM_EMU_CDOFFS, - .flags = CLKDM_CAN_HWSUP, + .flags = CLKDM_CAN_SWSUP, }; From mboxrd@z Thu Jan 1 00:00:00 1970 From: khilman@ti.com (Kevin Hilman) Date: Tue, 03 Apr 2012 16:14:19 -0700 Subject: oprofile and ARM A9 hardware counter In-Reply-To: <20120403160706.GP17741@mudshark.cambridge.arm.com> (Will Deacon's message of "Tue, 3 Apr 2012 17:07:06 +0100") References: <20120403092524.GD17741@mudshark.cambridge.arm.com> <20120403094749.GH17741@mudshark.cambridge.arm.com> <20120403123444.GL17741@mudshark.cambridge.arm.com> <878vicsxef.fsf@ti.com> <20120403160706.GP17741@mudshark.cambridge.arm.com> Message-ID: <87ehs4pfw4.fsf@ti.com> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org Will Deacon writes: [...] > Right. Can you confirm whether the PMU/CTI interrupts fire for you please? > Just run perf top and look at /proc/interrupts while it's running. You > should see a couple of arm-pmu entries in there and hopefully numbers > 0. Ah, I see now (I'm a perf newbie.) Indeed, like you, I have to change the EMU clock domain to SWSUP[1] in order to see any interrupts and see anything in perf top. This isn't really a mergeable workaround, so I'll look into this a little closer with Santosh to see what we can do once we fully understand the HW problem. Kevin [1] diff --git a/arch/arm/mach-omap2/clockdomains44xx_data.c b/arch/arm/mach-omap2/clockdomains44xx_data.c index 9299ac2..41d2260 100644 --- a/arch/arm/mach-omap2/clockdomains44xx_data.c +++ b/arch/arm/mach-omap2/clockdomains44xx_data.c @@ -390,7 +390,7 @@ static struct clockdomain emu_sys_44xx_clkdm = { .prcm_partition = OMAP4430_PRM_PARTITION, .cm_inst = OMAP4430_PRM_EMU_CM_INST, .clkdm_offs = OMAP4430_PRM_EMU_CM_EMU_CDOFFS, - .flags = CLKDM_CAN_HWSUP, + .flags = CLKDM_CAN_SWSUP, };