From: Kevin Hilman <khilman@ti.com>
To: javier Martin <javier.martin@vista-silicon.com>
Cc: linux-omap@vger.kernel.org, Koen Kooi <koen@beagleboard.org>
Subject: Re: cpuidle status in mainline for Beagleboard xM
Date: Thu, 01 Sep 2011 10:46:53 -0700 [thread overview]
Message-ID: <87ei00f94i.fsf@ti.com> (raw)
In-Reply-To: <CACKLOr0KpCUXrXM7M9YvE3DGPbGjzT4N678eEPfx_GGE7+40-w@mail.gmail.com> (javier Martin's message of "Thu, 1 Sep 2011 17:33:31 +0200")
javier Martin <javier.martin@vista-silicon.com> writes:
> Hi Kevin,
> thanks for your help.
>
>> CPU is staying in C0 probably because UARTs are not being idled, so SoC
>> cannot hit deeper idle states. Try the following at the command line to
>> to enable UART idle timeouts, so the SoC can attempt idle after the
>> timeout period
>>
>> # UART timeouts: omap-serial (4th UART only on OMAP36xx and OMAP4)
>> echo 5 > /sys/devices/platform/omap/omap_uart.0/sleep_timeout
>> echo 5 > /sys/devices/platform/omap/omap_uart.1/sleep_timeout
>> echo 5 > /sys/devices/platform/omap/omap_uart.2/sleep_timeout
>> echo 5 > /sys/devices/platform/omap/omap_uart.3/sleep_timeout
>>
>> After 5 seconds of inactivity on the UARTs, you should see the SoC
>> hitting deeper C-states.
>
> I've tried that but it still doesn't hit any C-state deeper than 0.
> I'll try the same test using your pm branch you pointed me out and
> post the results.
>
The CPUidle stuff works in mainline (after allowing UARTs to idle).
You only need my pm-wip/cpufreq branch for testing CPUfreq.
Kevin
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next prev parent reply other threads:[~2011-09-01 17:46 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2011-09-01 14:14 cpuidle status in mainline for Beagleboard xM javier Martin
2011-09-01 15:10 ` Kevin Hilman
2011-09-01 15:33 ` javier Martin
2011-09-01 17:46 ` Kevin Hilman [this message]
2011-09-02 6:05 ` Jarkko Nikula
2011-09-02 7:23 ` javier Martin
2011-09-02 17:14 ` Kevin Hilman
2011-09-05 8:04 ` javier Martin
2011-09-06 21:04 ` Kevin Hilman
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