From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3F34C23D7DF; Sat, 19 Sep 2026 09:33:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789810389; cv=none; b=gFnyxujcdqIG+qhmiXCBRuVrx9neyHfGiMk9FjGbYCSMY9zuw+Lw/8oKqKHqSlrcxX7SBSP0hcLo3wt7+o7KX2ksI3sDQATjdPMKs+QwWFAJmkINdcZ0IrcTmMrr7UTi7VRxLfhAgExnCGGGnZJy734/9kHh3IOPpPVYKXCqgQI= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789810389; c=relaxed/simple; bh=37Tkp54FuTweTIX79ZXQH1nZlgF0Y6dt687PbaKTug8=; h=Date:Message-ID:From:To:Cc:Subject:In-Reply-To:References: MIME-Version:Content-Type; b=IpFwy2hux1LJkdQU+ceK/Oc8lOr/MFXTJrgqj5z5UAUddW+TigQ7Odd2mQF/HH7EjcJ+TfyOng1JiMaSQHwLEf9JAYFBVKPtchm8YrDmuw9xxI9GqLcfmplnJLOA6mP+ASmdmuMjqV3GXbDk64/WwkMSl86HYJUfXo4S+tb31/k= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=XDsjrrlC; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="XDsjrrlC" Received: by smtp.kernel.org (Postfix) with ESMTPSA id C87281F000FF; Sat, 19 Sep 2026 09:33:07 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1789810387; bh=0caxOyaJoh8KN4zezLmE5kiSj3XpRezHw9bAKEfHF+E=; h=Date:From:To:Cc:Subject:In-Reply-To:References; b=XDsjrrlC/bjieVDUM7zOk8gB4UIJFl0ddaQ+sC2uP+/yLsu5viZfE67d6SlH0ixE1 qMAhmknJmMs7wGx8sQt27EdAOeDgKn1hK6JGmYWAbpkIcecakZ5L7iOHcB2tH23SJe X3FrTs3okSimGbCy3EAnHnLSh29C1NmKKzXLlSqFnEf06RizFeAvfziU3V9CKhGjbz n2XSP826Kn3M6DQ4nGxKzM439GmgWbwsKqsR25CJHdxO3IVh6AuKF5kw/EaLS+aYm/ tzHXNRduo/Mj4wn+pnsUqB+mrcuz6UClC7uu8bBQqoZf5N8Qa0Nx/ni3qeiTf0aIet FuUGVQfh4gWOQ== Received: from sofa.misterjones.org ([185.219.108.64] helo=lobster-girl.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.98.2) (envelope-from ) id 1x7rRR-0000000AvOn-27ai; Sat, 19 Sep 2026 09:33:05 +0000 Date: Sat, 19 Sep 2026 10:36:12 +0100 Message-ID: <87fqz54m7n.wl-maz@kernel.org> From: Marc Zyngier To: Sascha Bischoff Cc: "linux-arm-kernel@lists.infradead.org" , "kvmarm@lists.linux.dev" , "kvm@vger.kernel.org" , nd , "oliver.upton@linux.dev" , Joey Gouly , Suzuki Poulose , "yuzenghui@huawei.com" , "peter.maydell@linaro.org" , "lpieralisi@kernel.org" , Timothy Hayes , "fuad.tabba@linux.dev" Subject: Re: [PATCH v6 35/49] KVM: arm64: gic-v5: Implement save/restore mechanisms for ISTs In-Reply-To: <20260904113404.4051341-36-sascha.bischoff@arm.com> References: <20260904113404.4051341-1-sascha.bischoff@arm.com> <20260904113404.4051341-36-sascha.bischoff@arm.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/30.1 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: Sascha.Bischoff@arm.com, linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, kvm@vger.kernel.org, nd@arm.com, oliver.upton@linux.dev, Joey.Gouly@arm.com, Suzuki.Poulose@arm.com, yuzenghui@huawei.com, peter.maydell@linaro.org, lpieralisi@kernel.org, Timothy.Hayes@arm.com, fuad.tabba@linux.dev X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false On Fri, 04 Sep 2026 12:52:03 +0100, Sascha Bischoff wrote: Another LKP bot sparse finding at 202609191215.to1MBYak-lkp@intel.com: > +/* > + * Save a linear host IST to userspace memory. > + * > + * Only the architected 32-bit ISTE state is stored. Metadata is skipped when > + * striding through the host IST. > + */ > +static int vgic_v5_save_linear_ist(const struct vgic_v5_ist_desc *ist, > + u32 __user *uaddr, size_t nr_entries) > +{ > + __le32 h_iste; > + size_t index; > + int ret; > + > + vgic_v5_clean_inval(ist->base, > + GICV5_LINEAR_IST_SIZE(ist->id_bits, ist->istsz)); > + > + for (index = 0; index < nr_entries; index++) { > + __le32 *h_iste_addr = ist->base + index * ist->iste_size; > + > + h_iste = READ_ONCE(*h_iste_addr); > + ret = put_user(h_iste, uaddr); h_iste is an __le32, while uaddr is a pointer to u32. Not great, even if arm64 BE is now dead. I'll queue this: @@ -1459,7 +1459,6 @@ static int vgic_v5_get_lpi_ist_desc(struct kvm *kvm, static int vgic_v5_save_linear_ist(const struct vgic_v5_ist_desc *ist, u32 __user *uaddr, size_t nr_entries) { - __le32 h_iste; size_t index; int ret; @@ -1468,8 +1467,9 @@ static int vgic_v5_save_linear_ist(const struct vgic_v5_ist_desc *ist, for (index = 0; index < nr_entries; index++) { __le32 *h_iste_addr = ist->base + index * ist->iste_size; + u32 h_iste; - h_iste = READ_ONCE(*h_iste_addr); + h_iste = le32_to_cpu(READ_ONCE(*h_iste_addr)); ret = put_user(h_iste, uaddr); if (ret) return ret; Thanks, M. -- Jazz isn't dead. It just smells funny.