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Fri, 05 Dec 2025 01:28:59 -0800 (PST) Received: from draig.lan ([185.126.160.19]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-42f7cbe8fe8sm7670787f8f.2.2025.12.05.01.28.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 05 Dec 2025 01:28:59 -0800 (PST) Received: from draig (localhost [IPv6:::1]) by draig.lan (Postfix) with ESMTP id 4305F5F7F6; Fri, 05 Dec 2025 09:28:58 +0000 (GMT) From: =?utf-8?Q?Alex_Benn=C3=A9e?= To: Jessica Clarke Cc: qemu-devel@nongnu.org, Peter Maydell , "open list:ARM TCG CPUs" Subject: Re: [PATCH v3] target/arm: handle unaligned PC during tlb probe In-Reply-To: (Jessica Clarke's message of "Fri, 5 Dec 2025 01:28:53 +0000") References: <20251204203540.1381896-1-alex.bennee@linaro.org> User-Agent: mu4e 1.12.14-pre3; emacs 30.1 Date: Fri, 05 Dec 2025 09:28:58 +0000 Message-ID: <87fr9ps2ed.fsf@draig.linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=alex.bennee@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org Sender: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org Jessica Clarke writes: > On Thu, Dec 04, 2025 at 08:35:40PM +0000, Alex Benn=C3=A9e wrote: >> PC alignment faults have priority over instruction aborts and we have >> code to deal with this in the translation front-ends. However during >> tb_lookup we can see a potentially faulting probe which doesn't get a >> MemOp set. If the page isn't available this results in >> EC_INSNABORT (0x20) instead of EC_PCALIGNMENT (0x22). >>=20 >> As there is no easy way to set the appropriate MemOp in the >> instruction fetch probe path lets just detect it in >> arm_cpu_tlb_fill_align() ahead of the main alignment check. We also >> teach arm_deliver_fault to deliver the right syndrome for >> MMU_INST_FETCH alignment issues. >>=20 >> Fixes: https://gitlab.com/qemu-project/qemu/-/issues/3233 >> Tested-by: Jessica Clarke > > v3 is different enough from the tested RFC that maybe this shouldn't > have been carried forwards, but I've now tested this v3 and it does > indeed still fix the issue in my testing. I did re-test myself and figured it was only adding to the robustness but thanks for re-confirming its working for you. > > Thanks, > Jessica --=20 Alex Benn=C3=A9e Virtualisation Tech Lead @ Linaro