Re: Affinity setting problem for emulated MSI on PLIC

[Thomas Gleixner <tglx@linutronix.de>]

On Thu, Jul 24 2025 at 09:34, Inochi Amaoto wrote:
> On Thu, Jul 24, 2025 at 12:50:05AM +0200, Thomas Gleixner wrote:
>> May I ask the obvious question:
>> 
>>     How did this obviously disfunctional driver gain Tested-by and other
>>     relevant tags?
>
> I think the SG2042 pci driver does not support affinity setting, so it
> is ignored. But the detail thing I will cc Chen Wang. I guess he can give
> some details.

It does not matter whether the PCI part supports it or not.

PLIC definitely supports it and if the routing entry is not set up, then
there is no way that an interrupt is delivered. As the routing entry
write is delayed on startup until irq_enable() is invoked, this never
happens because of PCI/MSI not having a irq_enable() callback.

> For SG2044, I have tested at old version and it worked when submitting.
> And I guess it is because the commit [1], which remove the irq_set_affinity.
>
> [1] https://lore.kernel.org/r/20240723132958.41320-6-marek.vasut+renesas@mailbox.org
>
> IIRC, the worked version I tested has no affinity set and all irqs
> are routed to 0, which is different from the behavior now. Another

That does not make any sense. What sets the routing entry for CPU0?

This really needs a coherent explanation. Works by chance is not an
explanation at all :)

Thanks,

        tglx