From: Jani Nikula <jani.nikula@linux.intel.com>
To: Imre Deak <imre.deak@intel.com>,
intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org
Subject: Re: [PATCH 10/17] drm/i915/ddi: Add a helper to enable a port
Date: Wed, 05 Feb 2025 14:49:49 +0200 [thread overview]
Message-ID: <87frks4kuq.fsf@intel.com> (raw)
In-Reply-To: <20250129200221.2508101-11-imre.deak@intel.com>
On Wed, 29 Jan 2025, Imre Deak <imre.deak@intel.com> wrote:
> Add a helper to enable a port instead of open-coding it.
>
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_ddi.c | 34 +++++++++++-------------
> 1 file changed, 16 insertions(+), 18 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 73702ccbb3773..ddb182550ad0f 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -3057,6 +3057,17 @@ mtl_ddi_disable_d2d_link(struct intel_encoder *encoder)
> port_name(port));
> }
>
> +static void intel_enable_ddi_buf(struct intel_encoder *encoder, u32 buf_ctl)
This is in line with current code, but I'd use intel_ddi_buf_enable()
instead.
> +{
> + struct intel_display *display = to_intel_display(encoder);
> + enum port port = encoder->port;
> +
> + intel_de_write(display, DDI_BUF_CTL(port), buf_ctl | DDI_BUF_CTL_ENABLE);
> + intel_de_posting_read(display, DDI_BUF_CTL(port));
> +
> + intel_wait_ddi_buf_active(encoder);
> +}
> +
> static void intel_disable_ddi_buf(struct intel_encoder *encoder,
> const struct intel_crtc_state *crtc_state)
> {
> @@ -3375,7 +3386,7 @@ static void intel_ddi_enable_hdmi(struct intel_atomic_state *state,
> struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
> struct drm_connector *connector = conn_state->connector;
> enum port port = encoder->port;
> - u32 buf_ctl;
> + u32 buf_ctl = 0;
>
> if (!intel_hdmi_handle_sink_scrambling(encoder, connector,
> crtc_state->hdmi_high_tmds_clock_ratio,
> @@ -3440,8 +3451,6 @@ static void intel_ddi_enable_hdmi(struct intel_atomic_state *state,
> * is filled with lane count, already set in the crtc_state.
> * The same is required to be filled in PORT_BUF_CTL for C10/20 Phy.
> */
> - buf_ctl = DDI_BUF_CTL_ENABLE;
> -
> if (dig_port->lane_reversal)
> buf_ctl |= DDI_BUF_PORT_REVERSAL;
> if (dig_port->ddi_a_4_lanes)
> @@ -3467,9 +3476,7 @@ static void intel_ddi_enable_hdmi(struct intel_atomic_state *state,
> buf_ctl |= DDI_BUF_CTL_TC_PHY_OWNERSHIP;
> }
>
> - intel_de_write(dev_priv, DDI_BUF_CTL(port), buf_ctl);
> -
> - intel_wait_ddi_buf_active(encoder);
> + intel_enable_ddi_buf(encoder, buf_ctl);
> }
>
> static void intel_ddi_enable(struct intel_atomic_state *state,
> @@ -3692,7 +3699,6 @@ static void mtl_ddi_prepare_link_retrain(struct intel_dp *intel_dp,
> struct intel_display *display = to_intel_display(crtc_state);
> struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
> struct intel_encoder *encoder = &dig_port->base;
> - enum port port = encoder->port;
> u32 dp_tp_ctl;
>
> /*
> @@ -3726,15 +3732,11 @@ static void mtl_ddi_prepare_link_retrain(struct intel_dp *intel_dp,
> mtl_port_buf_ctl_program(encoder, crtc_state);
>
> /* 6.i Configure and enable DDI_CTL_DE to start sending valid data to port slice */
> - intel_dp->DP |= DDI_BUF_CTL_ENABLE;
> if (DISPLAY_VER(display) >= 20)
> intel_dp->DP |= XE2LPD_DDI_BUF_D2D_LINK_ENABLE;
>
> - intel_de_write(display, DDI_BUF_CTL(port), intel_dp->DP);
> - intel_de_posting_read(display, DDI_BUF_CTL(port));
> -
> - /* 6.j Poll for PORT_BUF_CTL Idle Status == 0, timeout after 100 us */
> - intel_wait_ddi_buf_active(encoder);
> + intel_enable_ddi_buf(encoder, intel_dp->DP);
> + intel_dp->DP |= DDI_BUF_CTL_ENABLE;
I hate this last line, but that's another story.
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> }
>
> static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp,
> @@ -3743,7 +3745,6 @@ static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp,
> struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
> struct intel_encoder *encoder = &dig_port->base;
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> - enum port port = encoder->port;
> u32 dp_tp_ctl;
>
> dp_tp_ctl = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state));
> @@ -3766,11 +3767,8 @@ static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp,
> (intel_tc_port_in_dp_alt_mode(dig_port) || intel_tc_port_in_legacy_mode(dig_port)))
> adlp_tbt_to_dp_alt_switch_wa(encoder);
>
> + intel_enable_ddi_buf(encoder, intel_dp->DP);
> intel_dp->DP |= DDI_BUF_CTL_ENABLE;
> - intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP);
> - intel_de_posting_read(dev_priv, DDI_BUF_CTL(port));
> -
> - intel_wait_ddi_buf_active(encoder);
> }
>
> static void intel_ddi_set_link_train(struct intel_dp *intel_dp,
--
Jani Nikula, Intel
next prev parent reply other threads:[~2025-02-05 12:50 UTC|newest]
Thread overview: 58+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-01-29 20:02 [PATCH 00/17] drm/i915/ddi: Fix/simplify port enabling/disabling Imre Deak
2025-01-29 20:02 ` [PATCH 01/17] drm/i915/dsi: Use TRANS_DDI_FUNC_CTL's own port width macro Imre Deak
2025-01-30 11:47 ` Jani Nikula
2025-01-29 20:02 ` [PATCH 02/17] drm/i915/ddi: Fix HDMI port width programming in DDI_BUF_CTL Imre Deak
2025-01-30 11:51 ` Jani Nikula
2025-01-30 13:33 ` Imre Deak
2025-01-29 20:02 ` [PATCH 03/17] drm/i915/ddi: Make all the PORT_WIDTH macros work the same way Imre Deak
2025-01-30 11:52 ` Jani Nikula
2025-01-29 20:02 ` [PATCH 04/17] drm/i915/ddi: Set missing TC DP PHY lane stagger delay in DDI_BUF_CTL Imre Deak
2025-02-05 12:22 ` Jani Nikula
2025-02-05 13:20 ` Imre Deak
2025-01-29 20:02 ` [PATCH 05/17] drm/i915/ddi: Simplify the port enabling via DDI_BUF_CTL Imre Deak
2025-01-30 11:55 ` Jani Nikula
2025-01-30 13:34 ` Imre Deak
2025-01-29 20:02 ` [PATCH 06/17] drm/i915/ddi: Simplify the port disabling " Imre Deak
2025-02-05 12:24 ` Jani Nikula
2025-01-29 20:02 ` [PATCH 07/17] drm/i915/ddi: Simplify waiting for a port to idle " Imre Deak
2025-02-05 12:35 ` Jani Nikula
2025-02-05 12:47 ` Imre Deak
2025-02-05 13:02 ` Jani Nikula
2025-02-12 11:48 ` Kahola, Mika
2025-01-29 20:02 ` [PATCH 08/17] drm/i915/ddi: Move platform checks within mtl_ddi_enable/disable_d2d_link() Imre Deak
2025-02-05 12:42 ` Jani Nikula
2025-02-05 13:46 ` Imre Deak
2025-01-29 20:02 ` [PATCH 09/17] drm/i915/ddi: Unify the platform specific functions disabling a port Imre Deak
2025-02-05 12:45 ` Jani Nikula
2025-01-29 20:02 ` [PATCH 10/17] drm/i915/ddi: Add a helper to enable " Imre Deak
2025-02-05 12:49 ` Jani Nikula [this message]
2025-02-05 14:43 ` Imre Deak
2025-01-29 20:02 ` [PATCH 11/17] drm/i915/ddi: Sanitize DDI_BUF_CTL register definitions Imre Deak
2025-02-05 12:52 ` Jani Nikula
2025-02-05 14:52 ` Imre Deak
2025-01-29 20:02 ` [PATCH 12/17] drm/i915/ddi: Configure/enable a port in DDI_BUF_CTL via read-modify-write Imre Deak
2025-02-10 18:13 ` Jani Nikula
2025-02-10 18:25 ` Imre Deak
2025-02-12 11:51 ` Kahola, Mika
2025-01-29 20:02 ` [PATCH 13/17] drm/i915/ddi: Factor out a helper to get DDI_BUF_CTL's config value Imre Deak
2025-02-10 18:06 ` Jani Nikula
2025-01-29 20:02 ` [PATCH 14/17] drm/i915/ddi: Reuse helper to compute the HDMI DDI_BUF_CTL config Imre Deak
2025-02-11 14:06 ` Kahola, Mika
2025-01-29 20:02 ` [PATCH 15/17] drm/i915/ddi: Reuse helper to compute the HDMI PORT_BUF_CTL1 config Imre Deak
2025-02-12 9:51 ` Kahola, Mika
2025-01-29 20:02 ` [PATCH 16/17] drm/i915/ddi: Move platform/encoder checks within adlp_tbt_to_dp_alt_switch_wa() Imre Deak
2025-02-12 11:06 ` Kahola, Mika
2025-01-29 20:02 ` [PATCH 17/17] drm/i915/ddi: Unify the platform specific functions enabling a port Imre Deak
2025-02-12 11:26 ` Kahola, Mika
2025-01-29 21:14 ` ✗ Fi.CI.CHECKPATCH: warning for drm/i915/ddi: Fix/simplify port enabling/disabling Patchwork
2025-01-29 21:14 ` ✗ Fi.CI.SPARSE: " Patchwork
2025-01-29 21:30 ` ✗ i915.CI.BAT: failure " Patchwork
2025-01-29 22:16 ` ✓ CI.Patch_applied: success " Patchwork
2025-01-29 22:17 ` ✗ CI.checkpatch: warning " Patchwork
2025-01-29 22:18 ` ✓ CI.KUnit: success " Patchwork
2025-01-29 22:34 ` ✓ CI.Build: " Patchwork
2025-01-29 22:37 ` ✓ CI.Hooks: " Patchwork
2025-01-29 22:38 ` ✗ CI.checksparse: warning " Patchwork
2025-01-30 6:22 ` ✓ Xe.CI.BAT: success " Patchwork
2025-01-30 8:27 ` ✗ Xe.CI.Full: failure " Patchwork
2025-01-31 7:42 ` Patchwork
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