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Thu, 16 Jan 2025 02:52:00 -0800 (PST) Received: from draig.lan ([85.9.250.243]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38a8e383dedsm20444054f8f.35.2025.01.16.02.51.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 16 Jan 2025 02:52:00 -0800 (PST) Received: from draig (localhost [IPv6:::1]) by draig.lan (Postfix) with ESMTP id 2EDE35F8B3; Thu, 16 Jan 2025 10:51:59 +0000 (GMT) From: =?utf-8?Q?Alex_Benn=C3=A9e?= To: Ilya Leoshkevich Cc: Richard Henderson , Paolo Bonzini , qemu-devel@nongnu.org, Nina Schoetterl-Glausch Subject: Re: [PATCH] accel/tcg: Call tcg_tb_insert() for one-insn TBs In-Reply-To: (Ilya Leoshkevich's message of "Thu, 16 Jan 2025 10:19:30 +0100") References: <20250115232022.27332-1-iii@linux.ibm.com> User-Agent: mu4e 1.12.8; emacs 29.4 Date: Thu, 16 Jan 2025 10:51:59 +0000 Message-ID: <87frljhvzk.fsf@draig.linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2a00:1450:4864:20::431; envelope-from=alex.bennee@linaro.org; helo=mail-wr1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Ilya Leoshkevich writes: > On Wed, 2025-01-15 at 16:08 -0800, Richard Henderson wrote: >> On 1/15/25 15:20, Ilya Leoshkevich wrote: >> > Currently single-insn TBs created from I/O memory are not added to >> > region_trees. Therefore, when they generate exceptions, they are >> > not >> > handled by cpu_restore_state_from_tb(). For x86 this is not a >> > problem, >> > because x86_restore_state_to_opc() only restores pc and cc, which >> > are >> > already correct. However, on several other architectures, >> > restore_state_to_opc() restores more registers, and guests can >> > notice >> > incorrect values. >> >=20 >> > Fix by always calling tcg_tb_insert(). This may increase the size >> > of >> > region_trees, but tcg_region_reset_all() clears it once >> > code_gen_buffer >> > fills up, so it will not grow uncontrollably. >> >=20 >> > Co-developed-by: Nina Schoetterl-Glausch >> > Signed-off-by: Ilya Leoshkevich >> > --- >>=20 >> This needs something else.=C2=A0 The reason why they're not insertted is >> that they're not valid=20 >> for a second execution.=C2=A0 We need to not find them in the search tre= e. > > I have the impression that code_gen_buffer is=C2=A0append-only, so after = we > create a new TB for the second execution, the first TB should not > be deleted - is this correct? At least I haven't found=C2=A0code_gen_ptr > decrements, besides the rollback at the end of tb_gen_code(). Then, > since region_trees are indexed by code_gen_buffer pointers, and not > guest pointers, this should not introduce any stale entries. We used to generate a temporary TB, execute it and then wind codeptr back. We simplified the code to generate the TB but then not add it to QHT - I think the original reasoning was saving on scarce CF_ flags and not over complicating the tb_gen_code function. See around 873d64ac30 (accel/tcg: re-factor non-RAM execution code). This does have the effect of potentially regenerating the same TB over and over again but usually there only a few insns executed out of IO space. However some arches do more of this than others. And now we have devices such as CXL where people do want to run large amounts of code directly out of io address space. This eventually exhausts the codegen buffer so we do a tb_flush() and start again. This is obviously sloooooow. > > While we might not need to find the ones created for the first > execution, we still need to find the ones for executions that fail - > and there is no way to tell in advance, which ones these are going to > be, so the idea here is to register all of them. > > Am I missing something? > >> r~ --=20 Alex Benn=C3=A9e Virtualisation Tech Lead @ Linaro