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From: Cornelia Huck <cohuck@redhat.com>
To: "Daniel P. Berrangé" <berrange@redhat.com>,
	"Marc Zyngier" <maz@kernel.org>
Cc: Kashyap Chamarthy <kchamart@redhat.com>,
	Eric Auger <eric.auger@redhat.com>,
	eric.auger.pro@gmail.com, qemu-devel@nongnu.org,
	qemu-arm@nongnu.org, kvmarm@lists.linux.dev,
	peter.maydell@linaro.org, richard.henderson@linaro.org,
	alex.bennee@linaro.org, oliver.upton@linux.dev,
	sebott@redhat.com, shameerali.kolothum.thodi@huawei.com,
	armbru@redhat.com, abologna@redhat.com, jdenemar@redhat.com,
	shahuang@redhat.com, mark.rutland@arm.com, philmd@linaro.org,
	pbonzini@redhat.com
Subject: Re: [PATCH RFCv2 00/20] kvm/arm: Introduce a customizable aarch64 KVM host model
Date: Fri, 20 Dec 2024 17:04:25 +0100	[thread overview]
Message-ID: <87frmibat2.fsf@redhat.com> (raw)
In-Reply-To: <Z2RdMJHydsvPpmdH@redhat.com>

On Thu, Dec 19 2024, Daniel P. Berrangé <berrange@redhat.com> wrote:

> On Thu, Dec 19, 2024 at 03:41:56PM +0000, Marc Zyngier wrote:
>> On Thu, 19 Dec 2024 15:07:25 +0000,
>> Kashyap Chamarthy <kchamart@redhat.com> wrote:
>> > 
>> > On Thu, Dec 19, 2024 at 12:26:29PM +0000, Marc Zyngier wrote:
>> > > On Thu, 19 Dec 2024 11:35:16 +0000,
>> > > Kashyap Chamarthy <kchamart@redhat.com> wrote:
>> > 
>> > [...]
>> > 
>> > > > Consider this:
>> > > > 
>> > > > Say, there's a serious security issue in a released ARM CPU.  As part of
>> > > > the fix, two new CPU flags need to be exposed to the guest OS, call them
>> > > > "secflag1" and "secflag2".  Here, the user is configuring a baseline
>> > > > model + two extra CPU flags, not to get close to some other CPU model
>> > > > but to mitigate itself against a serious security flaw.
>> > > 
>> > > If there's such a security issue, that the hypervisor's job to do so,
>> > > not userspace. 
>> > 
>> > I don't disagree.  Probably that has always been the case on ARM.  I
>> > asked the above based on how QEMU on x86 handles it today.
>> > 
>> > > See what KVM does for CSV3, for example (and all the
>> > > rest of the side-channel stuff).
>> > 
>> > Noted.  From a quick look in the kernel tree, I assume you're referring
>> > to these commits[1].
>> > 
>> > > You can't rely on userspace for security, that'd be completely
>> > > ludicrous.
>> > 
>> > As Dan Berrangé points out, it's the bog-standard way QEMU deals with
>> > some of the CPU-related issues on x86 today.  See this "important CPU
>> > flags"[2] section in the QEMU docs.
>> 
>> I had a look, and we do things quite differently. For example, the
>> spec-ctrl equivalent in implemented in FW and in KVM, and is exposed
>> by default if the HW is vulnerable. Userspace could hide that the
>> mitigation is there, but that's the extent of the configurability.
>
> Whether it is enabled by default or disabled by default isn't a
> totally fatal problem. If QEMU can toggle it to the opposite value,
> we have the same level of configurability in both cases.

I don't think "hiding" is the same thing as "disabling"? The underlying
behaviour will still have changed, the main question is whether that is
a problem.

>
> It does, however, have implications for QEMU as if KVM gained support
> for exposing the new feature by default and QEMU didn't know about
> it, then the guest ABI would have changed without QEMU realizing it.
>
> IOW, it would imply a requirement for timely QEMU updates to match
> the kernel, which is something we wouldn't need in x86 world where
> the feature is disabled by default. Disable by default is a more
> stable approach from QEMU's POV.

It implies that QEMU (or generally the VMM) needs to actively disable
everything it does not know about (i.e. setting everything in any
writable id reg to zero if it has no idea what it is about) to provide a
stable guest interface across different kernels. Just tweaking some
known values is only sufficient for a stable interface across two
systems with the same kernel.

(...)

>> That's why I don't see CPU models as a viable thing in terms of ABI.
>> They are an approximation of what you could have, but the ABI is
>> elsewhere.
>
> Right, this makes life quite challenging for QEMU. The premise of named
> CPU models (as opposed to -host), is to facilitate the migration of VMs
> between heterogenous hardware platforms. That assumes it is possible to
> downgrade the CPU on both src + dst, to the common baseline you desire.
>
> If we were to define a named CPU model, for that to be usable, QEMU
> would have to be able to query the "maxmimum" architectural features,
> and validate that the delta between the host maximum, and the named
> CPU model is possible to downgrade. Is arm providing sufficient info
> to let QEMU do that ?

Not sure if I understand what you mean, but "give me the contents of all
id registers, and which registers are writable" should probably do the
trick?


  reply	other threads:[~2024-12-20 16:04 UTC|newest]

Thread overview: 56+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-12-06 11:21 [PATCH RFCv2 00/20] kvm/arm: Introduce a customizable aarch64 KVM host model Cornelia Huck
2024-12-06 11:21 ` [PATCH RFCv2 01/20] kvm: kvm_get_writable_id_regs Cornelia Huck
2024-12-12 13:59   ` Richard Henderson
2024-12-12 14:12     ` Eric Auger
2024-12-13 15:43       ` Cornelia Huck
2024-12-06 11:21 ` [PATCH RFCv2 02/20] arm/cpu: Add sysreg definitions in cpu-sysregs.h Cornelia Huck
2024-12-12 14:37   ` Richard Henderson
2024-12-12 17:46     ` Eric Auger
2024-12-12 18:12       ` Richard Henderson
2024-12-13 16:16         ` Cornelia Huck
2024-12-06 11:21 ` [PATCH RFCv2 03/20] arm/cpu: Store aa64isar0 into the idregs arrays Cornelia Huck
2024-12-06 11:21 ` [PATCH RFCv2 04/20] arm/cpu: Store aa64isar1/2 into the idregs array Cornelia Huck
2024-12-06 11:21 ` [PATCH RFCv2 05/20] arm/cpu: Store aa64drf0/1 " Cornelia Huck
2024-12-06 11:21 ` [PATCH RFCv2 06/20] arm/cpu: Store aa64mmfr0-3 " Cornelia Huck
2024-12-06 11:22 ` [PATCH RFCv2 07/20] arm/cpu: Store aa64drf0/1 " Cornelia Huck
2024-12-06 11:22 ` [PATCH RFCv2 08/20] arm/cpu: Store aa64smfr0 " Cornelia Huck
2024-12-06 11:22 ` [PATCH RFCv2 09/20] arm/cpu: Store id_isar0-7 " Cornelia Huck
2024-12-06 11:22 ` [PATCH RFCv2 10/20] arm/cpu: Store id_mfr0/1 " Cornelia Huck
2024-12-06 11:22 ` [PATCH RFCv2 11/20] arm/cpu: Store id_dfr0/1 " Cornelia Huck
2024-12-06 11:22 ` [PATCH RFCv2 12/20] arm/cpu: Store id_mmfr0-5 " Cornelia Huck
2024-12-06 11:22 ` [PATCH RFCv2 13/20] arm/cpu: Add infra to handle generated ID register definitions Cornelia Huck
2024-12-06 11:22 ` [PATCH RFCv2 14/20] arm/cpu: Add sysreg generation scripts Cornelia Huck
2024-12-06 11:22 ` [PATCH RFCv2 15/20] arm/cpu: Add generated files Cornelia Huck
2024-12-06 11:22 ` [PATCH RFCv2 16/20] arm/kvm: Allow reading all the writable ID registers Cornelia Huck
2024-12-06 11:22 ` [PATCH RFCv2 17/20] arm/kvm: write back modified ID regs to KVM Cornelia Huck
2024-12-06 11:22 ` [PATCH RFCv2 18/20] arm/cpu: more customization for the kvm host cpu model Cornelia Huck
2024-12-06 11:22 ` [PATCH RFCv2 19/20] arm-qmp-cmds: introspection for ID register props Cornelia Huck
2024-12-06 11:22 ` [PATCH RFCv2 20/20] arm/cpu-features: document ID reg properties Cornelia Huck
2024-12-12  7:41 ` [PATCH RFCv2 00/20] kvm/arm: Introduce a customizable aarch64 KVM host model Eric Auger
2024-12-12  8:12 ` Eric Auger
2024-12-12  8:42   ` Eric Auger
2024-12-12 13:09     ` Shameerali Kolothum Thodi
2024-12-12 13:09       ` Shameerali Kolothum Thodi via
2024-12-12 13:29       ` Eric Auger
2024-12-12  9:10   ` Daniel P. Berrangé
2024-12-12  9:36     ` Cornelia Huck
2024-12-12 10:04       ` Eric Auger
2024-12-12 14:46         ` Cornelia Huck
2024-12-19 11:35         ` Kashyap Chamarthy
2024-12-19 12:26           ` Marc Zyngier
2024-12-19 12:38             ` Daniel P. Berrangé
2024-12-19 13:01               ` Marc Zyngier
2024-12-19 15:07             ` Kashyap Chamarthy
2024-12-19 15:41               ` Marc Zyngier
2024-12-19 17:51                 ` Daniel P. Berrangé
2024-12-20 16:04                   ` Cornelia Huck [this message]
2024-12-21 13:02                   ` Marc Zyngier
2024-12-20 11:52                 ` Kashyap Chamarthy
2024-12-20 16:17                   ` Cornelia Huck
2024-12-21 14:45                   ` Marc Zyngier
2024-12-16 16:42   ` Cornelia Huck
2024-12-16 16:58     ` Cornelia Huck
2024-12-12 13:13 ` Sebastian Ott
2024-12-12 14:46   ` Cornelia Huck
2024-12-17 15:21 ` Marc Zyngier
2024-12-17 18:05   ` Eric Auger

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