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<20241106085507.76425-7-bastien.curutchet@bootlin.com> (Bastien Curutchet's message of "Wed, 6 Nov 2024 09:55:07 +0100") References: <20241106085507.76425-1-bastien.curutchet@bootlin.com> <20241106085507.76425-7-bastien.curutchet@bootlin.com> User-Agent: mu4e 1.12.1; emacs 29.4 Date: Mon, 11 Nov 2024 20:32:09 +0100 Message-ID: <87frnxr2h2.fsf@bootlin.com> MIME-Version: 1.0 X-GND-Sasl: miquel.raynal@bootlin.com X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241111_113214_966283_01BF8516 X-CRM114-Status: GOOD ( 25.76 ) X-BeenThere: linux-mtd@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux MTD discussion mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Sender: "linux-mtd" Errors-To: linux-mtd-bounces+linux-mtd=archiver.kernel.org@lists.infradead.org SGkgQmFzdGllbiwKCk9uIDA2LzExLzIwMjQgYXQgMDk6NTU6MDcgKzAxLCBCYXN0aWVuIEN1cnV0 Y2hldCA8YmFzdGllbi5jdXJ1dGNoZXRAYm9vdGxpbi5jb20+IHdyb3RlOgoKPiBUaGUgc2V0dXBf aW50ZXJmYWNlKCkgb3BlcmF0aW9uIGlzbid0IGltcGxlbWVudGVkLiBJdCBmb3JjZXMgdGhlIGRy aXZlcgo+IHRvIHVzZSB0aGUgT05GSSBtb2RlIDAsIHRob3VnaCBpdCBjb3VsZCB1c2UgbW9yZSBv cHRpbWFsIG1vZGVzLgo+Cj4gSW1wbGVtZW50IHRoZSBzZXR1cF9pbnRlcmZhY2UoKSBvcGVyYXRp b24uIEl0IHVzZXMgdGhlCj4gYWVtaWZfc2V0X2NzX3RpbWluZ3MoKSBmdW5jdGlvbiBmcm9tIHRo ZSBBRU1JRiBkcml2ZXIgdG8gdXBkYXRlIHRoZQo+IGNoaXAgc2VsZWN0IHRpbWluZ3MuIFRoZSBj YWxjdWxhdGlvbiBvZiB0aGUgcmVnaXN0ZXIncyBjb250ZW50cyBpcwo+IGRpcmVjdGx5IGV4dHJh Y3RlZCBmcm9tIMKnMjAuMy4yLjMgb2YgdGhlIERhVmluY2kgVFJNIFsxXQo+Cj4gVGhlc2UgdGlt aW5ncyBhcmUgcHJldmlvdXNseSBzZXQgYnkgdGhlIEFFTUlGIGRyaXZlciBpdHNlbGYgZnJvbQo+ IGRldmljZS10cmVlIHByb3BlcnRpZXMuIFRoZXJlZm9yZSwgSU1ITywgZmFpbGluZyB0byB1cGRh dGUgdGhlbSBpbiB0aGUKPiBzZXR1cF9pbnRlcmZhY2UoKSBpc24ndCBjcml0aWNhbCwgd2hpY2gg aXMgd2h5IDAgaXMgcmV0dXJuZWQgZXZlbiB3aGVuCj4gdGltaW5ncyBhcmVuJ3QgdXBkYXRlZC4K CkRpZCB5b3UgZXhwZXJpZW5jZSBmYWlsdXJlcz8gQmVjYXVzZSBJJ2QgYmUgbW9yZSBjb25zZXJ2 YXRpdmUgYW5kIGVycm9yCm91dCBsb3VkbHkgd2hlbiBzb21ldGhpbmcgaXMgd3JvbmcuIEluIGdl bmVyYWwgaXQgaXMgYSBzYWZlc3QgYXBwcm9hY2gKb24gdGhlIGxvbmcgdGVybS4gSGVyZSBtYXli ZSB5b3UgaGF2ZSBnb29kIHJlYXNvbnMgdG8gZG8gZGlmZmVyZW50bHksIGluCnRoaXMgY2FzZSBJ IGFtIGFsbCBlYXJzLgoKPiBNQVhfVEhfUFMgYW5kIE1BWF9UU1VfUFMgYXJlIHRoZSB3b3JzdCBj YXNlIHRpbWluZ3MgYmFzZWQgb24gdGhlCj4gS2V5c3RvbmUyIGFuZCBEYVZpbmNpIGRhdGFzaGVl dHMuCj4KPiBbMV0gOiBodHRwczovL3d3dy50aS5jb20vbGl0L3VnL3NwcnVoNzdjL3NwcnVoNzdj LnBkZgo+Cj4gU2lnbmVkLW9mZi1ieTogQmFzdGllbiBDdXJ1dGNoZXQgPGJhc3RpZW4uY3VydXRj aGV0QGJvb3RsaW4uY29tPgo+IC0tLQo+ICBkcml2ZXJzL210ZC9uYW5kL3Jhdy9kYXZpbmNpX25h bmQuYyB8IDc4ICsrKysrKysrKysrKysrKysrKysrKysrKysrKysrCj4gIDEgZmlsZSBjaGFuZ2Vk LCA3OCBpbnNlcnRpb25zKCspCj4KPiBkaWZmIC0tZ2l0IGEvZHJpdmVycy9tdGQvbmFuZC9yYXcv ZGF2aW5jaV9uYW5kLmMgYi9kcml2ZXJzL210ZC9uYW5kL3Jhdy9kYXZpbmNpX25hbmQuYwo+IGlu ZGV4IDU2MzA0NWM3Y2UwOC4uMmQwYzU2NGM4ZDE3IDEwMDY0NAo+IC0tLSBhL2RyaXZlcnMvbXRk L25hbmQvcmF3L2RhdmluY2lfbmFuZC5jCj4gKysrIGIvZHJpdmVycy9tdGQvbmFuZC9yYXcvZGF2 aW5jaV9uYW5kLmMKPiBAQCAtMTQsNiArMTQsNyBAQAo+ICAjaW5jbHVkZSA8bGludXgvZXJyLmg+ Cj4gICNpbmNsdWRlIDxsaW51eC9pb3BvbGwuaD4KPiAgI2luY2x1ZGUgPGxpbnV4L2tlcm5lbC5o Pgo+ICsjaW5jbHVkZSA8bGludXgvbWVtb3J5L3RpLWFlbWlmLmg+Cj4gICNpbmNsdWRlIDxsaW51 eC9tb2R1bGUuaD4KPiAgI2luY2x1ZGUgPGxpbnV4L210ZC9yYXduYW5kLmg+Cj4gICNpbmNsdWRl IDxsaW51eC9tdGQvcGFydGl0aW9ucy5oPgo+IEBAIC00NCw2ICs0NSw5IEBACj4gICNkZWZpbmUJ TUFTS19BTEUJCTB4MDgKPiAgI2RlZmluZQlNQVNLX0NMRQkJMHgxMAo+ICAKPiArI2RlZmluZSBN QVhfVFNVX1BTCQkzMDAwCS8qIElucHV0IHNldHVwIHRpbWUgaW4gcHMgKi8KPiArI2RlZmluZSBN QVhfVEhfUFMJCTE2MDAJLyogSW5wdXQgaG9sZCB0aW1lIGluIHBzICovCj4gKwo+ICBzdHJ1Y3Qg ZGF2aW5jaV9uYW5kX3BkYXRhIHsKPiAgCXVpbnQzMl90CQltYXNrX2FsZTsKPiAgCXVpbnQzMl90 CQltYXNrX2NsZTsKPiBAQCAtMTIwLDYgKzEyNCw3IEBAIHN0cnVjdCBkYXZpbmNpX25hbmRfaW5m byB7Cj4gIAl1aW50MzJfdAkJY29yZV9jaGlwc2VsOwo+ICAKPiAgCXN0cnVjdCBjbGsJCSpjbGs7 Cj4gKwlzdHJ1Y3QgYWVtaWZfZGV2aWNlCSphZW1pZjsKPiAgfTsKPiAgCj4gIHN0YXRpYyBERUZJ TkVfU1BJTkxPQ0soZGF2aW5jaV9uYW5kX2xvY2spOwo+IEBAIC03NjcsOSArNzcyLDgxIEBAIHN0 YXRpYyBpbnQgZGF2aW5jaV9uYW5kX2V4ZWNfb3Aoc3RydWN0IG5hbmRfY2hpcCAqY2hpcCwKPiAg CXJldHVybiAwOwo+ICB9Cj4gIAo+ICsjZGVmaW5lIFRPX0NZQ0xFUyhwcywgcGVyaW9kX25zKSAo RElWX1JPVU5EX1VQKChwcykgLyAxMDAwLCAocGVyaW9kX25zKSkpCj4gKwo+ICtzdGF0aWMgaW50 IGRhdmluY2lfbmFuZF9zZXR1cF9pbnRlcmZhY2Uoc3RydWN0IG5hbmRfY2hpcCAqY2hpcCwgaW50 IGNoaXBuciwKPiArCQkJCQljb25zdCBzdHJ1Y3QgbmFuZF9pbnRlcmZhY2VfY29uZmlnICpjb25m KQo+ICt7Cj4gKwlzdHJ1Y3QgZGF2aW5jaV9uYW5kX2luZm8gKmluZm8gPSB0b19kYXZpbmNpX25h bmQobmFuZF90b19tdGQoY2hpcCkpOwo+ICsJY29uc3Qgc3RydWN0IG5hbmRfc2RyX3RpbWluZ3Mg KnNkcjsKPiArCXN0cnVjdCBhZW1pZl9jc190aW1pbmdzIHRpbWluZ3M7Cj4gKwlzMzIgY2ZnLCBt aW4sIGN5Y19uczsKPiArCj4gKwljeWNfbnMgPSAxMDAwMDAwMDAwIC8gY2xrX2dldF9yYXRlKGlu Zm8tPmNsayk7Cj4gKwo+ICsJc2RyID0gbmFuZF9nZXRfc2RyX3RpbWluZ3MoY29uZik7Cj4gKwlp ZiAoSVNfRVJSKHNkcikpCj4gKwkJcmV0dXJuIFBUUl9FUlIoc2RyKTsKPiArCj4gKwljZmcgPSBU T19DWUNMRVMoc2RyLT50Q0xSX21pbiwgY3ljX25zKSAtIDE7Cj4gKwl0aW1pbmdzLnJzZXR1cCA9 IGNmZyA+IDAgPyBjZmcgOiAwOwo+ICsKPiArCWNmZyA9IG1heF90KHMzMiwgVE9fQ1lDTEVTKHNk ci0+dFJFQV9tYXggKyBNQVhfVFNVX1BTLCBjeWNfbnMpLAo+ICsJCSAgICBUT19DWUNMRVMoc2Ry LT50UlBfbWluLCBjeWNfbnMpKSAtIDE7Cj4gKwl0aW1pbmdzLnJzdHJvYmUgPSBjZmcgPiAwID8g Y2ZnIDogMDsKPiArCj4gKwltaW4gPSBUT19DWUNMRVMoc2RyLT50Q0VBX21heCArIE1BWF9UU1Vf UFMsIGN5Y19ucykgLSAyOwo+ICsJd2hpbGUgKChzMzIpKHRpbWluZ3MucnNldHVwICsgdGltaW5n cy5yc3Ryb2JlKSA8IG1pbikKPiArCQl0aW1pbmdzLnJzdHJvYmUrKzsKCkkgc2VlIGEgbG90IG9m IHdoaWxlIGxvb3BzIHdoaWNoIGp1c3Qgc3RvcCBpZiB5b3UgcmVhY2ggYSBtaW4vbWF4LCBJCmJl bGlldmUgYSBzbGlnaHRseSBtb3JlIHJvYnVzdCBhcHByb2FjaCBzaG91bGQgYmUgYXR0ZW1wdGVk LCBhbmQKcmV0dXJuaW5nIGVycm9ycyB3aGVuIHRoZXNlIGxpbWl0cyBhcmUgY3Jvc3NlZCB3b3Vs ZCBiZSBwcm9iYWJseQpiZW5lZmljaWFsIG9uIHRoZSBsb25nIHRlcm0/Cgo+ICsKPiArCWNmZyA9 IFRPX0NZQ0xFUygoczMyKShNQVhfVEhfUFMgLSBzZHItPnRDSFpfbWF4KSwgY3ljX25zKSAtIDE7 Cj4gKwl0aW1pbmdzLnJob2xkID0gY2ZnID4gMCA/IGNmZyA6IDA7Cj4gKwo+ICsJbWluID0gVE9f Q1lDTEVTKHNkci0+dFJDX21pbiwgY3ljX25zKSAtIDM7Cj4gKwl3aGlsZSAoKHMzMikodGltaW5n cy5yc2V0dXAgKyB0aW1pbmdzLnJzdHJvYmUgKyB0aW1pbmdzLnJob2xkKSA8IG1pbikKPiArCQl0 aW1pbmdzLnJob2xkKys7Cj4gKwo+ICsJY2ZnID0gVE9fQ1lDTEVTKChzMzIpKHNkci0+dFJIWl9t YXggLSAodGltaW5ncy5yaG9sZCArIDEpICogY3ljX25zICogMTAwMCksIGN5Y19ucyk7Cj4gKwlj ZmcgPSBtYXhfdChzMzIsIGNmZywgVE9fQ1lDTEVTKHNkci0+dENIWl9tYXgsIGN5Y19ucykpIC0g MTsKPiArCXRpbWluZ3MudGEgPSBjZmcgPiAwID8gY2ZnIDogMDsKPiArCj4gKwljZmcgPSBUT19D WUNMRVMoc2RyLT50V1BfbWluLCBjeWNfbnMpIC0gMTsKPiArCXRpbWluZ3Mud3N0cm9iZSA9IGNm ZyA+IDAgPyBjZmcgOiAwOwo+ICsKPiArCWNmZyA9IG1heF90KHMzMiwgVE9fQ1lDTEVTKHNkci0+ dENMU19taW4sIGN5Y19ucyksIFRPX0NZQ0xFUyhzZHItPnRBTFNfbWluLCBjeWNfbnMpKTsKPiAr CWNmZyA9IG1heF90KHMzMiwgY2ZnLCBUT19DWUNMRVMoc2RyLT50Q1NfbWluLCBjeWNfbnMpKSAt IDE7Cj4gKwl0aW1pbmdzLndzZXR1cCA9IGNmZyA+IDAgPyBjZmcgOiAwOwo+ICsKPiArCW1pbiA9 IFRPX0NZQ0xFUyhzZHItPnREU19taW4sIGN5Y19ucykgLSAyOwo+ICsJd2hpbGUgKChzMzIpKHRp bWluZ3Mud3NldHVwICsgdGltaW5ncy53c3Ryb2JlKSA8IG1pbikKPiArCQl0aW1pbmdzLndzdHJv YmUrKzsKPiArCj4gKwljZmcgPSBtYXhfdChzMzIsIFRPX0NZQ0xFUyhzZHItPnRDTEhfbWluLCBj eWNfbnMpLCBUT19DWUNMRVMoc2RyLT50QUxIX21pbiwgY3ljX25zKSk7Cj4gKwljZmcgPSBtYXhf dChzMzIsIGNmZywgVE9fQ1lDTEVTKHNkci0+dENIX21pbiwgY3ljX25zKSk7Cj4gKwljZmcgPSBt YXhfdChzMzIsIGNmZywgVE9fQ1lDTEVTKHNkci0+dERIX21pbiwgY3ljX25zKSkgLSAxOwo+ICsJ dGltaW5ncy53aG9sZCA9IGNmZyA+IDAgPyBjZmcgOiAwOwo+ICsKPiArCW1pbiA9IFRPX0NZQ0xF UyhzZHItPnRXQ19taW4sIGN5Y19ucykgLSAyOwo+ICsJd2hpbGUgKChzMzIpKHRpbWluZ3Mud3Nl dHVwICsgdGltaW5ncy53c3Ryb2JlICsgdGltaW5ncy53aG9sZCkgPCBtaW4pCj4gKwkJdGltaW5n cy53aG9sZCsrOwo+ICsKPiArCWRldl9kYmcoJmluZm8tPnBkZXYtPmRldiwgIlJTRVRVUCAleCBS U1RST0JFICV4IFJIT0xEICV4XG4iLAo+ICsJCXRpbWluZ3MucnNldHVwLCB0aW1pbmdzLnJzdHJv YmUsIHRpbWluZ3MucmhvbGQpOwo+ICsJZGV2X2RiZygmaW5mby0+cGRldi0+ZGV2LCAiVEEgJXhc biIsIHRpbWluZ3MudGEpOwo+ICsJZGV2X2RiZygmaW5mby0+cGRldi0+ZGV2LCAiV1NFVFVQICV4 IFdTVFJPQkUgJXggV0hPTEQgJXhcbiIsCj4gKwkJdGltaW5ncy53c2V0dXAsIHRpbWluZ3Mud3N0 cm9iZSwgdGltaW5ncy53aG9sZCk7Cj4gKwoKSGVyZSB5b3UgcHJvYmFibHkgd2FudCB0byBleGl0 IGluIHRoZSBOQU5EX0RBVEFfSUZBQ0VfQ0hFQ0tfT05MWSBjYXNlLgoKPiArCWlmIChhZW1pZl9z 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Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="A37qSliz" Received: by mail.gandi.net (Postfix) with ESMTPSA id AB2391C0003; Mon, 11 Nov 2024 19:32:10 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1731353531; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=kGFoL8GPN97aScIvx4frLGVFiInxEXUkie6Iu4YEKqA=; b=A37qSliz/4dvnRXOM94JvGMkgKahiGnxzTrNawpwjjYv/Dua5RC/s/yz5wNwWmQiKnu4R7 1naQGK7kTgFly4hghfdukaLF4uSL9AaoOiSnq309FGtot4FoKgxBsBDHKbSTvb2EQxkLDU Mqy3OhUXvx906Iz89YuNHyQTLaSupkebR2CTahsT4keEsPV3pr37hCxnT4KrPkuUjLzXYR wKvlJChrbQ8ntJog2iP2HTWWbs+ffst3wKwrvFPAw7VUy5H39uYg8gb8gucAXHpbyTCK2H mscodQLkm7Wv9fO7FbLKbRXqAW7JmmYCGM057v9d8GuuXz7V05/efFgGDLdUsw== From: Miquel Raynal To: Bastien Curutchet Cc: Santosh Shilimkar , Krzysztof Kozlowski , Richard Weinberger , Vignesh Raghavendra , linux-kernel@vger.kernel.org, linux-mtd@lists.infradead.org, Thomas Petazzoni , Herve Codina , Christopher Cordahi Subject: Re: [PATCH v2 6/6] mtd: rawnand: davinci: Implement setup_interface() operation In-Reply-To: <20241106085507.76425-7-bastien.curutchet@bootlin.com> (Bastien Curutchet's message of "Wed, 6 Nov 2024 09:55:07 +0100") References: <20241106085507.76425-1-bastien.curutchet@bootlin.com> <20241106085507.76425-7-bastien.curutchet@bootlin.com> User-Agent: mu4e 1.12.1; emacs 29.4 Date: Mon, 11 Nov 2024 20:32:09 +0100 Message-ID: <87frnxr2h2.fsf@bootlin.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable X-GND-Sasl: miquel.raynal@bootlin.com Hi Bastien, On 06/11/2024 at 09:55:07 +01, Bastien Curutchet wrote: > The setup_interface() operation isn't implemented. It forces the driver > to use the ONFI mode 0, though it could use more optimal modes. > > Implement the setup_interface() operation. It uses the > aemif_set_cs_timings() function from the AEMIF driver to update the > chip select timings. The calculation of the register's contents is > directly extracted from =C2=A720.3.2.3 of the DaVinci TRM [1] > > These timings are previously set by the AEMIF driver itself from > device-tree properties. Therefore, IMHO, failing to update them in the > setup_interface() isn't critical, which is why 0 is returned even when > timings aren't updated. Did you experience failures? Because I'd be more conservative and error out loudly when something is wrong. In general it is a safest approach on the long term. Here maybe you have good reasons to do differently, in this case I am all ears. > MAX_TH_PS and MAX_TSU_PS are the worst case timings based on the > Keystone2 and DaVinci datasheets. > > [1] : https://www.ti.com/lit/ug/spruh77c/spruh77c.pdf > > Signed-off-by: Bastien Curutchet > --- > drivers/mtd/nand/raw/davinci_nand.c | 78 +++++++++++++++++++++++++++++ > 1 file changed, 78 insertions(+) > > diff --git a/drivers/mtd/nand/raw/davinci_nand.c b/drivers/mtd/nand/raw/d= avinci_nand.c > index 563045c7ce08..2d0c564c8d17 100644 > --- a/drivers/mtd/nand/raw/davinci_nand.c > +++ b/drivers/mtd/nand/raw/davinci_nand.c > @@ -14,6 +14,7 @@ > #include > #include > #include > +#include > #include > #include > #include > @@ -44,6 +45,9 @@ > #define MASK_ALE 0x08 > #define MASK_CLE 0x10 >=20=20 > +#define MAX_TSU_PS 3000 /* Input setup time in ps */ > +#define MAX_TH_PS 1600 /* Input hold time in ps */ > + > struct davinci_nand_pdata { > uint32_t mask_ale; > uint32_t mask_cle; > @@ -120,6 +124,7 @@ struct davinci_nand_info { > uint32_t core_chipsel; >=20=20 > struct clk *clk; > + struct aemif_device *aemif; > }; >=20=20 > static DEFINE_SPINLOCK(davinci_nand_lock); > @@ -767,9 +772,81 @@ static int davinci_nand_exec_op(struct nand_chip *ch= ip, > return 0; > } >=20=20 > +#define TO_CYCLES(ps, period_ns) (DIV_ROUND_UP((ps) / 1000, (period_ns))) > + > +static int davinci_nand_setup_interface(struct nand_chip *chip, int chip= nr, > + const struct nand_interface_config *conf) > +{ > + struct davinci_nand_info *info =3D to_davinci_nand(nand_to_mtd(chip)); > + const struct nand_sdr_timings *sdr; > + struct aemif_cs_timings timings; > + s32 cfg, min, cyc_ns; > + > + cyc_ns =3D 1000000000 / clk_get_rate(info->clk); > + > + sdr =3D nand_get_sdr_timings(conf); > + if (IS_ERR(sdr)) > + return PTR_ERR(sdr); > + > + cfg =3D TO_CYCLES(sdr->tCLR_min, cyc_ns) - 1; > + timings.rsetup =3D cfg > 0 ? cfg : 0; > + > + cfg =3D max_t(s32, TO_CYCLES(sdr->tREA_max + MAX_TSU_PS, cyc_ns), > + TO_CYCLES(sdr->tRP_min, cyc_ns)) - 1; > + timings.rstrobe =3D cfg > 0 ? cfg : 0; > + > + min =3D TO_CYCLES(sdr->tCEA_max + MAX_TSU_PS, cyc_ns) - 2; > + while ((s32)(timings.rsetup + timings.rstrobe) < min) > + timings.rstrobe++; I see a lot of while loops which just stop if you reach a min/max, I believe a slightly more robust approach should be attempted, and returning errors when these limits are crossed would be probably beneficial on the long term? > + > + cfg =3D TO_CYCLES((s32)(MAX_TH_PS - sdr->tCHZ_max), cyc_ns) - 1; > + timings.rhold =3D cfg > 0 ? cfg : 0; > + > + min =3D TO_CYCLES(sdr->tRC_min, cyc_ns) - 3; > + while ((s32)(timings.rsetup + timings.rstrobe + timings.rhold) < min) > + timings.rhold++; > + > + cfg =3D TO_CYCLES((s32)(sdr->tRHZ_max - (timings.rhold + 1) * cyc_ns * = 1000), cyc_ns); > + cfg =3D max_t(s32, cfg, TO_CYCLES(sdr->tCHZ_max, cyc_ns)) - 1; > + timings.ta =3D cfg > 0 ? cfg : 0; > + > + cfg =3D TO_CYCLES(sdr->tWP_min, cyc_ns) - 1; > + timings.wstrobe =3D cfg > 0 ? cfg : 0; > + > + cfg =3D max_t(s32, TO_CYCLES(sdr->tCLS_min, cyc_ns), TO_CYCLES(sdr->tAL= S_min, cyc_ns)); > + cfg =3D max_t(s32, cfg, TO_CYCLES(sdr->tCS_min, cyc_ns)) - 1; > + timings.wsetup =3D cfg > 0 ? cfg : 0; > + > + min =3D TO_CYCLES(sdr->tDS_min, cyc_ns) - 2; > + while ((s32)(timings.wsetup + timings.wstrobe) < min) > + timings.wstrobe++; > + > + cfg =3D max_t(s32, TO_CYCLES(sdr->tCLH_min, cyc_ns), TO_CYCLES(sdr->tAL= H_min, cyc_ns)); > + cfg =3D max_t(s32, cfg, TO_CYCLES(sdr->tCH_min, cyc_ns)); > + cfg =3D max_t(s32, cfg, TO_CYCLES(sdr->tDH_min, cyc_ns)) - 1; > + timings.whold =3D cfg > 0 ? cfg : 0; > + > + min =3D TO_CYCLES(sdr->tWC_min, cyc_ns) - 2; > + while ((s32)(timings.wsetup + timings.wstrobe + timings.whold) < min) > + timings.whold++; > + > + dev_dbg(&info->pdev->dev, "RSETUP %x RSTROBE %x RHOLD %x\n", > + timings.rsetup, timings.rstrobe, timings.rhold); > + dev_dbg(&info->pdev->dev, "TA %x\n", timings.ta); > + dev_dbg(&info->pdev->dev, "WSETUP %x WSTROBE %x WHOLD %x\n", > + timings.wsetup, timings.wstrobe, timings.whold); > + Here you probably want to exit in the NAND_DATA_IFACE_CHECK_ONLY case. > + if (aemif_set_cs_timings(info->aemif, info->core_chipsel, &timings) < 0) > + dev_info(&info->pdev->dev, > + "Failed to dynamically update the CS timings, keep them unchanged"); > + > + return 0; > +} > + Thanks, Miqu=C3=A8l