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From: Thomas Gleixner <tglx@linutronix.de>
To: Bjorn Helgaas <helgaas@kernel.org>, Dullfire <dullfire@yahoo.com>
Cc: davem@davemloft.net, sparclinux@vger.kernel.org,
	netdev@vger.kernel.org, linux-pci@vger.kernel.org
Subject: Re: Kernel panic with niu module
Date: Wed, 06 Nov 2024 16:36:21 +0100	[thread overview]
Message-ID: <87fro4pe6i.ffs@tglx> (raw)
In-Reply-To: <20241104234412.GA1446170@bhelgaas>

On Mon, Nov 04 2024 at 17:44, Bjorn Helgaas wrote:
> On Mon, Nov 04, 2024 at 05:34:42AM -0600, Dullfire wrote:
>> I have also bisected the kernel, and determined that  upstream commit
>> 7d5ec3d3612396dc6d4b76366d20ab9fc06f399f revealed this issue. This commit
>> adds read to the mask status before any write to PCI_MSIX_ENTRY_DATA, thus
>> provoking the issue.

7d5ec3d36123 had the mask_all() invocation _before_ setting up the the
entries and reading back the descriptors. So that commit cannot break
the niu device when your problem analysis is correct.

83dbf898a2d4 moved the mask_all() invocation after setting up MSI-X into
the success path to handle a bonkers Marvell NVME device. That then
matches your problem desription as the read proceeds the write.

I've never heard of a similiar problem, so I'm pretty sure that's truly
niu specific.

Thanks,

        tglx

  parent reply	other threads:[~2024-11-06 15:36 UTC|newest]

Thread overview: 7+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
     [not found] <f7c43842-270e-48f8-ba89-9b5e67910131.ref@yahoo.com>
2024-11-04 11:34 ` Kernel panic with niu module Dullfire
2024-11-04 23:44   ` Bjorn Helgaas
2024-11-05 11:24     ` Dullfire
2024-11-06 15:36     ` Thomas Gleixner [this message]
2024-11-06 16:04       ` Dullfire
2024-11-06 17:32         ` Thomas Gleixner
2024-11-06 22:12           ` Dullfire

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