Re: [Intel-gfx] [PATCH] drm/i915/display: Add a separate crtc_enable hook for SKL+

[Jani Nikula <jani.nikula@intel.com>]

On Wed, 11 May 2022, Manasi Navare <manasi.d.navare@intel.com> wrote:
> Currently we reuse hsw_crtc_enable for SKL+ platforms.
> But this has added a lot of platform checks for SKL+ platforms.
> So its time to move the code to a separate crtc_enable hook
> for SKL+ platforms.

This leaves behind a ton of unused code paths in hsw_crtc_enable, which
needs cleanup.

BR,
Jani.

>
> No functional changes here.
>
> Suggested-by: Jani Nikula <jani.nikula@intel.com>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Cc: Jani Nikula <jani.nikula@intel.com>
> Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display.c | 74 +++++++++++++++++++-
>  1 file changed, 73 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 806d50b302ab..e2e228073e2e 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -1895,6 +1895,78 @@ static void hsw_configure_cpu_transcoder(const struct intel_crtc_state *crtc_sta
>  	hsw_set_transconf(crtc_state);
>  }
>  
> +static void skl_crtc_enable(struct intel_atomic_state *state,
> +			    struct intel_crtc *crtc)
> +{
> +	const struct intel_crtc_state *new_crtc_state =
> +		intel_atomic_get_new_crtc_state(state, crtc);
> +	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> +	enum pipe pipe = crtc->pipe;
> +	enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder;
> +	bool psl_clkgate_wa;
> +
> +	if (drm_WARN_ON(&dev_priv->drm, crtc->active))
> +		return;
> +
> +	if (!new_crtc_state->bigjoiner_pipes) {
> +		intel_encoders_pre_pll_enable(state, crtc);
> +
> +		if (new_crtc_state->shared_dpll)
> +			intel_enable_shared_dpll(new_crtc_state);
> +
> +		intel_encoders_pre_enable(state, crtc);
> +	} else {
> +		icl_ddi_bigjoiner_pre_enable(state, new_crtc_state);
> +	}
> +
> +	intel_dsc_enable(new_crtc_state);
> +
> +	if (DISPLAY_VER(dev_priv) >= 13)
> +		intel_uncompressed_joiner_enable(new_crtc_state);
> +
> +	intel_set_pipe_src_size(new_crtc_state);
> +	bdw_set_pipemisc(new_crtc_state);
> +
> +	if (!intel_crtc_is_bigjoiner_slave(new_crtc_state) &&
> +	    !transcoder_is_dsi(cpu_transcoder))
> +		hsw_configure_cpu_transcoder(new_crtc_state);
> +
> +	crtc->active = true;
> +
> +	/* Display WA #1180: WaDisableScalarClockGating: glk */
> +	psl_clkgate_wa = DISPLAY_VER(dev_priv) == 10 &&
> +		new_crtc_state->pch_pfit.enabled;
> +	if (psl_clkgate_wa)
> +		glk_pipe_scaler_clock_gating_wa(dev_priv, pipe, true);
> +
> +	skl_pfit_enable(new_crtc_state);
> +
> +	/*
> +	 * On ILK+ LUT must be loaded before the pipe is running but with
> +	 * clocks enabled
> +	 */
> +	intel_color_load_luts(new_crtc_state);
> +	intel_color_commit_noarm(new_crtc_state);
> +	intel_color_commit_arm(new_crtc_state);
> +
> +	hsw_set_linetime_wm(new_crtc_state);
> +
> +	if (DISPLAY_VER(dev_priv) >= 11)
> +		icl_set_pipe_chicken(new_crtc_state);
> +
> +	intel_initial_watermarks(state, crtc);
> +
> +	if (intel_crtc_is_bigjoiner_slave(new_crtc_state))
> +		intel_crtc_vblank_on(new_crtc_state);
> +
> +	intel_encoders_enable(state, crtc);
> +
> +	if (psl_clkgate_wa) {
> +		intel_crtc_wait_for_next_vblank(crtc);
> +		glk_pipe_scaler_clock_gating_wa(dev_priv, pipe, false);
> +	}
> +}
> +
>  static void hsw_crtc_enable(struct intel_atomic_state *state,
>  			    struct intel_crtc *crtc)
>  {
> @@ -9231,7 +9303,7 @@ static const struct drm_mode_config_funcs intel_mode_funcs = {
>  
>  static const struct drm_i915_display_funcs skl_display_funcs = {
>  	.get_pipe_config = hsw_get_pipe_config,
> -	.crtc_enable = hsw_crtc_enable,
> +	.crtc_enable = skl_crtc_enable,
>  	.crtc_disable = hsw_crtc_disable,
>  	.commit_modeset_enables = skl_commit_modeset_enables,
>  	.get_initial_plane_config = skl_get_initial_plane_config,

-- 
Jani Nikula, Intel Open Source Graphics Center