From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 515A6C433F5 for ; Wed, 8 Dec 2021 13:43:06 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Subject:Cc:To:From:Message-ID:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=QuViAMQMBwvKxlWsxTgA3A0rs1nj3TB0Js5RJ8iSVkY=; b=Y92jI8XjjGdEym cjObypknveAS1xcnX+ie9k6h4R51TP1DfizqpFcHrXFdkBkYQmiUJ8xViHW1MVpwen+ivDlrBI5cu W9wl42Uhj8kJqts2hmk3bzRwZq9JZ7CKIArLTFXNPl+4oHN/IWEbKEUYfzIOZyQwI0bV0o+EQR8mQ Hp5WIBepA3GQXfD2uqzPcI76zuFyHkBkW7QCJ7ndG9AB1v8fF+2rvdL8OOfv5xxQ5BL+OkPmwDMTA B8rvOCwu+5knKUYK5dZjSZ7M5IkewMbPZlqr00NlyR3xli919gmTEKSC08C/BroFubSEHsxo3lLq/ QbgDndMp3Q5zsphk7UVQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1muxCT-00CpV9-20; Wed, 08 Dec 2021 13:41:37 +0000 Received: from sin.source.kernel.org ([2604:1380:40e1:4800::1]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1muxCO-00CpTa-2i for linux-arm-kernel@lists.infradead.org; Wed, 08 Dec 2021 13:41:34 +0000 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by sin.source.kernel.org (Postfix) with ESMTPS id 59252CE216C; Wed, 8 Dec 2021 13:41:30 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 85E4CC00446; Wed, 8 Dec 2021 13:41:28 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1638970888; bh=OZzG9mnI07oghn5FHCCn22rzmq6jbRMNjzZzcon7K5k=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=ehoOHaw/MOpOucsXUIk2iiupzIAmlcanjnHqswDErS3uB7Q9XXJ/peLyc1qey+XH5 H0iEHIKfx7wqxSWCPpIygORpjvrARA95+ptfPSs5Mf135Cw8F0ekTOKPeDUTUh+XYi 37khwRyB/O9zstxFMS7XH+hwlQh0bc2fsxtT9HJWYTzh55nuQw6+Ck9XHmGgvvXffp XZLQG8j+WTakZx1GB0iQ42NEmKWwhLLtyWgRtW5qMeC2aNzfi6Bo8FZV8UdaKtc02h SCibHf5r7UQnM6acJt/zcmywAmUeiVhp/kzQVtqPRwx/N1h4KMY8GLDf0VGl2qQuKj VT9v3XZnnvFfA== Received: from sofa.misterjones.org ([185.219.108.64] helo=why.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1muxCI-00AmHF-LW; Wed, 08 Dec 2021 13:41:26 +0000 Date: Wed, 08 Dec 2021 13:41:26 +0000 Message-ID: <87fsr31aex.wl-maz@kernel.org> From: Marc Zyngier To: Alexandre Torgue Cc: Thomas Gleixner , Rob Herring , , , , Subject: Re: [PATCH 2/3] irqchip/stm32-exti: add STM32MP13 support In-Reply-To: <20211208130456.4002-3-alexandre.torgue@foss.st.com> References: <20211208130456.4002-1-alexandre.torgue@foss.st.com> <20211208130456.4002-3-alexandre.torgue@foss.st.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/27.1 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: alexandre.torgue@foss.st.com, tglx@linutronix.de, robh+dt@kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, devicetree@vger.kernel.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211208_054132_747092_D1439E09 X-CRM114-Status: GOOD ( 21.84 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Wed, 08 Dec 2021 13:04:55 +0000, Alexandre Torgue wrote: > > Enhance stm32-exti driver to support STM32MP13 SoC. This SoC uses the same > hardware version than STM32MP15. Only EXTI line mapping is changed and > following EXTI lines are supported: GPIO, RTC, I2C[1-5], UxART[1-8], > USBH_EHCI, USBH_OHCI, USB_OTG, LPTIM[1-5], ETH[1-2]. > > Signed-off-by: Alexandre Torgue > > diff --git a/drivers/irqchip/irq-stm32-exti.c b/drivers/irqchip/irq-stm32-exti.c > index b7cb2da71888..9d18f47040eb 100644 > --- a/drivers/irqchip/irq-stm32-exti.c > +++ b/drivers/irqchip/irq-stm32-exti.c > @@ -214,6 +214,48 @@ static const struct stm32_desc_irq stm32mp1_desc_irq[] = { > { .exti = 73, .irq_parent = 129, .chip = &stm32_exti_h_chip }, > }; > > +static const struct stm32_desc_irq stm32mp13_desc_irq[] = { > + { .exti = 0, .irq_parent = 6, .chip = &stm32_exti_h_chip }, > + { .exti = 1, .irq_parent = 7, .chip = &stm32_exti_h_chip }, > + { .exti = 2, .irq_parent = 8, .chip = &stm32_exti_h_chip }, > + { .exti = 3, .irq_parent = 9, .chip = &stm32_exti_h_chip }, > + { .exti = 4, .irq_parent = 10, .chip = &stm32_exti_h_chip }, > + { .exti = 5, .irq_parent = 24, .chip = &stm32_exti_h_chip }, > + { .exti = 6, .irq_parent = 65, .chip = &stm32_exti_h_chip }, > + { .exti = 7, .irq_parent = 66, .chip = &stm32_exti_h_chip }, > + { .exti = 8, .irq_parent = 67, .chip = &stm32_exti_h_chip }, > + { .exti = 9, .irq_parent = 68, .chip = &stm32_exti_h_chip }, > + { .exti = 10, .irq_parent = 41, .chip = &stm32_exti_h_chip }, > + { .exti = 11, .irq_parent = 43, .chip = &stm32_exti_h_chip }, > + { .exti = 12, .irq_parent = 77, .chip = &stm32_exti_h_chip }, > + { .exti = 13, .irq_parent = 78, .chip = &stm32_exti_h_chip }, > + { .exti = 14, .irq_parent = 106, .chip = &stm32_exti_h_chip }, > + { .exti = 15, .irq_parent = 109, .chip = &stm32_exti_h_chip }, > + { .exti = 16, .irq_parent = 1, .chip = &stm32_exti_h_chip }, > + { .exti = 19, .irq_parent = 3, .chip = &stm32_exti_h_chip_direct }, > + { .exti = 21, .irq_parent = 32, .chip = &stm32_exti_h_chip_direct }, > + { .exti = 22, .irq_parent = 34, .chip = &stm32_exti_h_chip_direct }, > + { .exti = 23, .irq_parent = 73, .chip = &stm32_exti_h_chip_direct }, > + { .exti = 24, .irq_parent = 93, .chip = &stm32_exti_h_chip_direct }, > + { .exti = 25, .irq_parent = 114, .chip = &stm32_exti_h_chip_direct }, > + { .exti = 26, .irq_parent = 38, .chip = &stm32_exti_h_chip_direct }, > + { .exti = 27, .irq_parent = 39, .chip = &stm32_exti_h_chip_direct }, > + { .exti = 28, .irq_parent = 40, .chip = &stm32_exti_h_chip_direct }, > + { .exti = 29, .irq_parent = 72, .chip = &stm32_exti_h_chip_direct }, > + { .exti = 30, .irq_parent = 53, .chip = &stm32_exti_h_chip_direct }, > + { .exti = 31, .irq_parent = 54, .chip = &stm32_exti_h_chip_direct }, > + { .exti = 32, .irq_parent = 83, .chip = &stm32_exti_h_chip_direct }, > + { .exti = 33, .irq_parent = 84, .chip = &stm32_exti_h_chip_direct }, > + { .exti = 44, .irq_parent = 96, .chip = &stm32_exti_h_chip_direct }, > + { .exti = 47, .irq_parent = 92, .chip = &stm32_exti_h_chip_direct }, > + { .exti = 48, .irq_parent = 116, .chip = &stm32_exti_h_chip_direct }, > + { .exti = 50, .irq_parent = 117, .chip = &stm32_exti_h_chip_direct }, > + { .exti = 52, .irq_parent = 118, .chip = &stm32_exti_h_chip_direct }, > + { .exti = 53, .irq_parent = 119, .chip = &stm32_exti_h_chip_direct }, > + { .exti = 68, .irq_parent = 63, .chip = &stm32_exti_h_chip_direct }, > + { .exti = 70, .irq_parent = 98, .chip = &stm32_exti_h_chip_direct }, > +}; Why does the driver need to carry these tables? This sort of information should really come from DT, instead of being hardcoded in the driver and bloating it for no reason. This all has a funny taste of the board files we used to have pre-DT. M. -- Without deviation from the norm, progress is not possible. _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B5129C433F5 for ; Wed, 8 Dec 2021 13:41:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234349AbhLHNpE (ORCPT ); Wed, 8 Dec 2021 08:45:04 -0500 Received: from sin.source.kernel.org ([145.40.73.55]:39722 "EHLO sin.source.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232209AbhLHNpE (ORCPT ); Wed, 8 Dec 2021 08:45:04 -0500 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by sin.source.kernel.org (Postfix) with ESMTPS id 864EACE2186; Wed, 8 Dec 2021 13:41:30 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 85E4CC00446; Wed, 8 Dec 2021 13:41:28 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1638970888; bh=OZzG9mnI07oghn5FHCCn22rzmq6jbRMNjzZzcon7K5k=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=ehoOHaw/MOpOucsXUIk2iiupzIAmlcanjnHqswDErS3uB7Q9XXJ/peLyc1qey+XH5 H0iEHIKfx7wqxSWCPpIygORpjvrARA95+ptfPSs5Mf135Cw8F0ekTOKPeDUTUh+XYi 37khwRyB/O9zstxFMS7XH+hwlQh0bc2fsxtT9HJWYTzh55nuQw6+Ck9XHmGgvvXffp XZLQG8j+WTakZx1GB0iQ42NEmKWwhLLtyWgRtW5qMeC2aNzfi6Bo8FZV8UdaKtc02h SCibHf5r7UQnM6acJt/zcmywAmUeiVhp/kzQVtqPRwx/N1h4KMY8GLDf0VGl2qQuKj VT9v3XZnnvFfA== Received: from sofa.misterjones.org ([185.219.108.64] helo=why.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1muxCI-00AmHF-LW; Wed, 08 Dec 2021 13:41:26 +0000 Date: Wed, 08 Dec 2021 13:41:26 +0000 Message-ID: <87fsr31aex.wl-maz@kernel.org> From: Marc Zyngier To: Alexandre Torgue Cc: Thomas Gleixner , Rob Herring , , , , Subject: Re: [PATCH 2/3] irqchip/stm32-exti: add STM32MP13 support In-Reply-To: <20211208130456.4002-3-alexandre.torgue@foss.st.com> References: <20211208130456.4002-1-alexandre.torgue@foss.st.com> <20211208130456.4002-3-alexandre.torgue@foss.st.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/27.1 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: alexandre.torgue@foss.st.com, tglx@linutronix.de, robh+dt@kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, devicetree@vger.kernel.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On Wed, 08 Dec 2021 13:04:55 +0000, Alexandre Torgue wrote: > > Enhance stm32-exti driver to support STM32MP13 SoC. This SoC uses the same > hardware version than STM32MP15. Only EXTI line mapping is changed and > following EXTI lines are supported: GPIO, RTC, I2C[1-5], UxART[1-8], > USBH_EHCI, USBH_OHCI, USB_OTG, LPTIM[1-5], ETH[1-2]. > > Signed-off-by: Alexandre Torgue > > diff --git a/drivers/irqchip/irq-stm32-exti.c b/drivers/irqchip/irq-stm32-exti.c > index b7cb2da71888..9d18f47040eb 100644 > --- a/drivers/irqchip/irq-stm32-exti.c > +++ b/drivers/irqchip/irq-stm32-exti.c > @@ -214,6 +214,48 @@ static const struct stm32_desc_irq stm32mp1_desc_irq[] = { > { .exti = 73, .irq_parent = 129, .chip = &stm32_exti_h_chip }, > }; > > +static const struct stm32_desc_irq stm32mp13_desc_irq[] = { > + { .exti = 0, .irq_parent = 6, .chip = &stm32_exti_h_chip }, > + { .exti = 1, .irq_parent = 7, .chip = &stm32_exti_h_chip }, > + { .exti = 2, .irq_parent = 8, .chip = &stm32_exti_h_chip }, > + { .exti = 3, .irq_parent = 9, .chip = &stm32_exti_h_chip }, > + { .exti = 4, .irq_parent = 10, .chip = &stm32_exti_h_chip }, > + { .exti = 5, .irq_parent = 24, .chip = &stm32_exti_h_chip }, > + { .exti = 6, .irq_parent = 65, .chip = &stm32_exti_h_chip }, > + { .exti = 7, .irq_parent = 66, .chip = &stm32_exti_h_chip }, > + { .exti = 8, .irq_parent = 67, .chip = &stm32_exti_h_chip }, > + { .exti = 9, .irq_parent = 68, .chip = &stm32_exti_h_chip }, > + { .exti = 10, .irq_parent = 41, .chip = &stm32_exti_h_chip }, > + { .exti = 11, .irq_parent = 43, .chip = &stm32_exti_h_chip }, > + { .exti = 12, .irq_parent = 77, .chip = &stm32_exti_h_chip }, > + { .exti = 13, .irq_parent = 78, .chip = &stm32_exti_h_chip }, > + { .exti = 14, .irq_parent = 106, .chip = &stm32_exti_h_chip }, > + { .exti = 15, .irq_parent = 109, .chip = &stm32_exti_h_chip }, > + { .exti = 16, .irq_parent = 1, .chip = &stm32_exti_h_chip }, > + { .exti = 19, .irq_parent = 3, .chip = &stm32_exti_h_chip_direct }, > + { .exti = 21, .irq_parent = 32, .chip = &stm32_exti_h_chip_direct }, > + { .exti = 22, .irq_parent = 34, .chip = &stm32_exti_h_chip_direct }, > + { .exti = 23, .irq_parent = 73, .chip = &stm32_exti_h_chip_direct }, > + { .exti = 24, .irq_parent = 93, .chip = &stm32_exti_h_chip_direct }, > + { .exti = 25, .irq_parent = 114, .chip = &stm32_exti_h_chip_direct }, > + { .exti = 26, .irq_parent = 38, .chip = &stm32_exti_h_chip_direct }, > + { .exti = 27, .irq_parent = 39, .chip = &stm32_exti_h_chip_direct }, > + { .exti = 28, .irq_parent = 40, .chip = &stm32_exti_h_chip_direct }, > + { .exti = 29, .irq_parent = 72, .chip = &stm32_exti_h_chip_direct }, > + { .exti = 30, .irq_parent = 53, .chip = &stm32_exti_h_chip_direct }, > + { .exti = 31, .irq_parent = 54, .chip = &stm32_exti_h_chip_direct }, > + { .exti = 32, .irq_parent = 83, .chip = &stm32_exti_h_chip_direct }, > + { .exti = 33, .irq_parent = 84, .chip = &stm32_exti_h_chip_direct }, > + { .exti = 44, .irq_parent = 96, .chip = &stm32_exti_h_chip_direct }, > + { .exti = 47, .irq_parent = 92, .chip = &stm32_exti_h_chip_direct }, > + { .exti = 48, .irq_parent = 116, .chip = &stm32_exti_h_chip_direct }, > + { .exti = 50, .irq_parent = 117, .chip = &stm32_exti_h_chip_direct }, > + { .exti = 52, .irq_parent = 118, .chip = &stm32_exti_h_chip_direct }, > + { .exti = 53, .irq_parent = 119, .chip = &stm32_exti_h_chip_direct }, > + { .exti = 68, .irq_parent = 63, .chip = &stm32_exti_h_chip_direct }, > + { .exti = 70, .irq_parent = 98, .chip = &stm32_exti_h_chip_direct }, > +}; Why does the driver need to carry these tables? This sort of information should really come from DT, instead of being hardcoded in the driver and bloating it for no reason. This all has a funny taste of the board files we used to have pre-DT. M. -- Without deviation from the norm, progress is not possible.