From: Mika Kuoppala <mika.kuoppala@linux.intel.com>
To: Chris Wilson <chris@chris-wilson.co.uk>, intel-gfx@lists.freedesktop.org
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Subject: Re: [Intel-gfx] [PATCH] drm/i915/gt: Reset execlists registers before HWSP
Date: Wed, 13 May 2020 12:32:37 +0300 [thread overview]
Message-ID: <87ftc42n9m.fsf@gaia.fi.intel.com> (raw)
In-Reply-To: <20200513085934.9859-1-chris@chris-wilson.co.uk>
Chris Wilson <chris@chris-wilson.co.uk> writes:
> Upon gt resume, we first poison then sanitize the engine. However, our
> testing shows that gen9 will very rarely retain the poisoned value from
> the HWSP mappings of the execlists status registers. This suggests that
> it is reading back from the HWSP, so rejig the register reset.
>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Acked-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_lrc.c | 19 +++++++++++++------
> 1 file changed, 13 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
> index 3d0e0894c015..a7d644a21f14 100644
> --- a/drivers/gpu/drm/i915/gt/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
> @@ -3924,6 +3924,14 @@ static void reset_csb_pointers(struct intel_engine_cs *engine)
>
> ring_set_paused(engine, 0);
>
> + /*
> + * Sometimes Icelake forgets to reset its pointers on a GPU reset.
> + * Bludgeon them with a mmio update to be sure.
> + */
> + ENGINE_WRITE(engine, RING_CONTEXT_STATUS_PTR,
> + reset_value << 8 | reset_value);
> + ENGINE_POSTING_READ(engine, RING_CONTEXT_STATUS_PTR);
> +
> /*
> * After a reset, the HW starts writing into CSB entry [0]. We
> * therefore have to set our HEAD pointer back one entry so that
> @@ -3937,16 +3945,15 @@ static void reset_csb_pointers(struct intel_engine_cs *engine)
> WRITE_ONCE(*execlists->csb_write, reset_value);
> wmb(); /* Make sure this is visible to HW (paranoia?) */
>
> - /*
> - * Sometimes Icelake forgets to reset its pointers on a GPU reset.
> - * Bludgeon them with a mmio update to be sure.
> - */
> + invalidate_csb_entries(&execlists->csb_status[0],
> + &execlists->csb_status[reset_value]);
> +
> + /* Once more for luck and our trusty paranoia */
> ENGINE_WRITE(engine, RING_CONTEXT_STATUS_PTR,
> reset_value << 8 | reset_value);
> ENGINE_POSTING_READ(engine, RING_CONTEXT_STATUS_PTR);
>
> - invalidate_csb_entries(&execlists->csb_status[0],
> - &execlists->csb_status[reset_value]);
> + GEM_BUG_ON(READ_ONCE(*execlists->csb_write) != reset_value);
> }
>
> static void execlists_sanitize(struct intel_engine_cs *engine)
> --
> 2.20.1
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next prev parent reply other threads:[~2020-05-13 9:34 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-05-13 8:59 [Intel-gfx] [PATCH] drm/i915/gt: Reset execlists registers before HWSP Chris Wilson
2020-05-13 9:32 ` Mika Kuoppala [this message]
2020-05-13 9:46 ` Chris Wilson
2020-05-13 9:34 ` [Intel-gfx] ✗ Fi.CI.BAT: failure for " Patchwork
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