[Qemu-arm] QEMU user mode for cortex M

[Qemu-arm] QEMU user mode for cortex M

[Massimiliano Cialdi]

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hello,
I would like to try some algorithms on cortex M (especially cortex M4). I
don't need to emulate the whole machine, I just need the user mode.
To test the feasibility, I wrote the trivial "hello world".

I can compile it with arm-none-eabi-gcc, but the newlib associated with it
does not implement any syscall.
So I tried, on ubuntu, with the cross compiler arm-linux-gnueabihf-gcc and
its libc6, but the latter is only distributed for cortex A.

What do you suggest? Should I recompile the libc6 for cortex M (or do I
find it pre-compiled)? Should I implement (and how?) syscalls on newlib?

In summary, I would need a step-by-step guide to running Cortex M code on
QEMU arm user mode.

best regards
Max

-- 
Et nunc, auxilium solis, vincam!
Oppugnatio solaris!
VIS!

Massimiliano Cialdi
cialdi@gmail.com

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Re: [Qemu-arm] QEMU user mode for cortex M

[Peter Maydell]

On Thu, 14 Mar 2019 at 22:30, Massimiliano Cialdi <cialdi@gmail.com> wrote:
>
> hello,
> I would like to try some algorithms on cortex M (especially cortex M4). I don't need to emulate the whole machine, I just need the user mode.
> To test the feasibility, I wrote the trivial "hello world".
>
> I can compile it with arm-none-eabi-gcc, but the newlib associated with it does not implement any syscall.
> So I tried, on ubuntu, with the cross compiler arm-linux-gnueabihf-gcc and its libc6, but the latter is only distributed for cortex A.
>
> What do you suggest? Should I recompile the libc6 for cortex M (or do I find it pre-compiled)? Should I implement (and how?) syscalls on newlib?
>
> In summary, I would need a step-by-step guide to running Cortex M code on QEMU arm user mode.

User-mode in Cortex-M is a weird thing to do, because what QEMU
gives you is the A-profile Linux syscalls. It's a hybrid that
we only continue to provide because it happens to be used and
useful to the gcc folks doing compiler testing. I would
recommend against using it, personally.

System emulation mode will get you something that actually
works the way the real hardware does. You can then do
output either via the UART or via semihosting (you need to
enable the latter on the commandline).

thanks
-- PMM

Re: [Qemu-arm] QEMU user mode for cortex M

[Alex Bennée]

Peter Maydell <peter.maydell@linaro.org> writes:

> On Thu, 14 Mar 2019 at 22:30, Massimiliano Cialdi <cialdi@gmail.com> wrote:
>>
>> hello,
>> I would like to try some algorithms on cortex M (especially cortex M4). I don't need to emulate the whole machine, I just need the user mode.
>> To test the feasibility, I wrote the trivial "hello world".
>>
>> I can compile it with arm-none-eabi-gcc, but the newlib associated with it does not implement any syscall.
>> So I tried, on ubuntu, with the cross compiler arm-linux-gnueabihf-gcc and its libc6, but the latter is only distributed for cortex A.
>>
>> What do you suggest? Should I recompile the libc6 for cortex M (or do I find it pre-compiled)? Should I implement (and how?) syscalls on newlib?
>>
>> In summary, I would need a step-by-step guide to running Cortex M code on QEMU arm user mode.
>
> User-mode in Cortex-M is a weird thing to do, because what QEMU
> gives you is the A-profile Linux syscalls.
<snip>
> System emulation mode will get you something that actually
> works the way the real hardware does. You can then do
> output either via the UART or via semihosting (you need to
> enable the latter on the commandline).

We've recently added the ability to compile system-mode tests although
we currently only have one test for Cortex-M0 (see
tests/tcg/test-armv6m-undef.s). However if you could write a boot.S for
cortex-m4 with a semihosting __sys_outc and link it with
tests/tcg/minilib then you have a reasonable test harness for building C
binaries (albeit without a proper libc) you can run with the system
emulator.

--
Alex Bennée

Re: [Qemu-arm] QEMU user mode for cortex M

[Massimiliano Cialdi]

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I have tried to follow some websites, such as, for example,
https://gnu-mcu-eclipse.github.io/qemu/options/,
http://sushihangover.github.io/arm-cortex-m-semihosting-with-qemu/ or
https://balau82.wordpress.com/2010/11/04/qemu-arm-semihosting/ without
success

I have my exetutable compiled with
/opt/gcc-arm-none-eabi-8-2018-q4-major/bin/arm-none-eabi-gcc -std=gnu11
-mcpu=cortex-m7 -mthumb -mfloat-abi=hard -mfpu=fpv5-d16 -fno-common
-specs=rdimon.specs -Wl,--cref,-Map=main.map main.c -o main.elf

then I try to execute qemu:
~/Downloads/qemu/qemu-3.1.0/arm-softmmu/qemu-system-arm -d
unimp,guest_errors -machine virt -monitor null -serial null  -semihosting
-nographic -semihosting-config enable=on,target=native -kernel main.elf
pflash_write: Unimplemented flash cmd sequence (offset 0000000003fffffc,
wcycle 0x0 cmd 0x0 value 0x80f7)
pflash_write: Unimplemented flash cmd sequence (offset 0000000003ffffcc,
wcycle 0x0 cmd 0x0 value 0xa984)
pflash_write: Unimplemented flash cmd sequence (offset 0000000003ffffd4,
wcycle 0x0 cmd 0x0 value 0x3)
pflash_write: Unimplemented flash cmd sequence (offset 0000000003ffffbc,
wcycle 0x0 cmd 0x0 value 0x1b368)
pflash_write: Unimplemented flash cmd sequence (offset 0000000003ffffc0,
wcycle 0x0 cmd 0x0 value 0x1b304)
pflash_write: Unimplemented flash cmd sequence (offset 0000000003ffffc4,
wcycle 0x0 cmd 0x0 value 0xa6cb)
pflash_write: Unimplemented flash cmd sequence (offset 000000000001b304,
wcycle 0x0 cmd 0x0 value 0x1)
pflash_write: Unimplemented flash cmd sequence (offset 0000000003ffff94,
wcycle 0x0 cmd 0x0 value 0x1b304)
pflash_write: Unimplemented flash cmd sequence (offset 0000000003ffffa4,
wcycle 0x0 cmd 0x0 value 0xa984)
pflash_write: Unimplemented flash cmd sequence (offset 0000000003ffffac,
wcycle 0x0 cmd 0x0 value 0xa617)
pflash_write: Unimplemented flash cmd sequence (offset 0000000003ffff6c,
wcycle 0x0 cmd 0x0 value 0x1b304)
pflash_write: Unimplemented flash cmd sequence (offset 0000000003ffff74,
wcycle 0x0 cmd 0x0 value 0x1)
pflash_write: Unimplemented flash cmd sequence (offset 0000000003ffff78,
wcycle 0x0 cmd 0x0 value 0x7ffffb4)
pflash_write: Unimplemented flash cmd sequence (offset 0000000003ffff84,
wcycle 0x0 cmd 0x0 value 0xa545)
pflash_write: Unimplemented flash cmd sequence (offset 000000000001aac0,
wcycle 0x0 cmd 0x0 value 0x18)
write access to unsupported AArch32 64 bit system register cp:12 opc1: 15
crm:8 (non-secure)


and nothing happend. Where am I wrong? I'm wrong at the compilation stage,
at the execution stage or both? Is there something wrong with the command
line parameters? Which one? How do I force a cortex-m4? How can I force the
Cpu without having to choose any machine?

best regards
Max

On Fri, Mar 15, 2019 at 11:05 AM Peter Maydell <peter.maydell@linaro.org>
wrote:

> On Thu, 14 Mar 2019 at 22:30, Massimiliano Cialdi <cialdi@gmail.com>
> wrote:
> >
> > hello,
> > I would like to try some algorithms on cortex M (especially cortex M4).
> I don't need to emulate the whole machine, I just need the user mode.
> > To test the feasibility, I wrote the trivial "hello world".
> >
> > I can compile it with arm-none-eabi-gcc, but the newlib associated with
> it does not implement any syscall.
> > So I tried, on ubuntu, with the cross compiler arm-linux-gnueabihf-gcc
> and its libc6, but the latter is only distributed for cortex A.
> >
> > What do you suggest? Should I recompile the libc6 for cortex M (or do I
> find it pre-compiled)? Should I implement (and how?) syscalls on newlib?
> >
> > In summary, I would need a step-by-step guide to running Cortex M code
> on QEMU arm user mode.
>
> User-mode in Cortex-M is a weird thing to do, because what QEMU
> gives you is the A-profile Linux syscalls. It's a hybrid that
> we only continue to provide because it happens to be used and
> useful to the gcc folks doing compiler testing. I would
> recommend against using it, personally.
>
> System emulation mode will get you something that actually
> works the way the real hardware does. You can then do
> output either via the UART or via semihosting (you need to
> enable the latter on the commandline).
>
> thanks
> -- PMM
>


-- 
Et nunc, auxilium solis, vincam!
Oppugnatio solaris!
VIS!

Massimiliano Cialdi
cialdi@gmail.com

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Re: [Qemu-arm] QEMU user mode for cortex M

[Alex Bennée]

Massimiliano Cialdi <cialdi@gmail.com> writes:

> I have tried to follow some websites, such as, for example,
> https://gnu-mcu-eclipse.github.io/qemu/options/,
> http://sushihangover.github.io/arm-cortex-m-semihosting-with-qemu/ or
> https://balau82.wordpress.com/2010/11/04/qemu-arm-semihosting/ without
> success
>
> I have my exetutable compiled with
> /opt/gcc-arm-none-eabi-8-2018-q4-major/bin/arm-none-eabi-gcc -std=gnu11
> -mcpu=cortex-m7 -mthumb -mfloat-abi=hard -mfpu=fpv5-d16 -fno-common
> -specs=rdimon.specs -Wl,--cref,-Map=main.map main.c -o main.elf

I thought you wanted to target a cortex-m4?

Have a look at how test-armv6m-undef is built. It is the simplest
dumbest M profile image you can build with a kernel that maps to 0 and a
simple reset vector at the start of the vector table:

>
> then I try to execute qemu:
> ~/Downloads/qemu/qemu-3.1.0/arm-softmmu/qemu-system-arm -d
> unimp,guest_errors -machine virt -monitor null -serial null  -semihosting
> -nographic -semihosting-config enable=on,target=native -kernel
> main.elf

I don't know what the virt machine defaults to for CPU but I'm fairly
sure it's not an m-profile CPU.
> write access to unsupported AArch32 64 bit system register cp:12 opc1: 15
> crm:8 (non-secure)
>
>
> and nothing happend. Where am I wrong? I'm wrong at the compilation stage,
> at the execution stage or both? Is there something wrong with the command
> line parameters? Which one? How do I force a cortex-m4? How can I force the
> Cpu without having to choose any machine?

It's hard to say without seeing what your test is doing. However I can force
a cortex-m4 on a microbit and run the following ok:

  ./qemu-system-arm  -monitor none -display none \
                     -chardev file,path=test-armv6m-undef.out,id=output \
                     -semihosting -M microbit \
                     -cpu cortex-m4 \
                     -kernel tests/test-armv6m-undef
                     -d in_asm,cpu,nochain


>
> best regards
> Max
>
> On Fri, Mar 15, 2019 at 11:05 AM Peter Maydell <peter.maydell@linaro.org>
> wrote:
>
>> On Thu, 14 Mar 2019 at 22:30, Massimiliano Cialdi <cialdi@gmail.com>
>> wrote:
>> >
>> > hello,
>> > I would like to try some algorithms on cortex M (especially cortex M4).
>> I don't need to emulate the whole machine, I just need the user mode.
>> > To test the feasibility, I wrote the trivial "hello world".
>> >
>> > I can compile it with arm-none-eabi-gcc, but the newlib associated with
>> it does not implement any syscall.
>> > So I tried, on ubuntu, with the cross compiler arm-linux-gnueabihf-gcc
>> and its libc6, but the latter is only distributed for cortex A.
>> >
>> > What do you suggest? Should I recompile the libc6 for cortex M (or do I
>> find it pre-compiled)? Should I implement (and how?) syscalls on newlib?
>> >
>> > In summary, I would need a step-by-step guide to running Cortex M code
>> on QEMU arm user mode.
>>
>> User-mode in Cortex-M is a weird thing to do, because what QEMU
>> gives you is the A-profile Linux syscalls. It's a hybrid that
>> we only continue to provide because it happens to be used and
>> useful to the gcc folks doing compiler testing. I would
>> recommend against using it, personally.
>>
>> System emulation mode will get you something that actually
>> works the way the real hardware does. You can then do
>> output either via the UART or via semihosting (you need to
>> enable the latter on the commandline).
>>
>> thanks
>> -- PMM
>>


--
Alex Bennée

Re: [Qemu-arm] QEMU user mode for cortex M

[Peter Maydell]

On Sat, 16 Mar 2019 at 12:01, Alex Bennée <alex.bennee@linaro.org> wrote:
> Massimiliano Cialdi <cialdi@gmail.com> writes:
> > then I try to execute qemu:
> > ~/Downloads/qemu/qemu-3.1.0/arm-softmmu/qemu-system-arm -d
> > unimp,guest_errors -machine virt -monitor null -serial null  -semihosting
> > -nographic -semihosting-config enable=on,target=native -kernel
> > main.elf
>
> I don't know what the virt machine defaults to for CPU but I'm fairly
> sure it's not an m-profile CPU.

Default is Cortex-A15. "virt" cannot handle M-profile CPUs.

> > write access to unsupported AArch32 64 bit system register cp:12 opc1: 15
> > crm:8 (non-secure)
> >
> >
> > and nothing happend. Where am I wrong? I'm wrong at the compilation stage,
> > at the execution stage or both? Is there something wrong with the command
> > line parameters? Which one? How do I force a cortex-m4? How can I force the
> > Cpu without having to choose any machine?
>
> It's hard to say without seeing what your test is doing. However I can force
> a cortex-m4 on a microbit and run the following ok:
>
>   ./qemu-system-arm  -monitor none -display none \
>                      -chardev file,path=test-armv6m-undef.out,id=output \
>                      -semihosting -M microbit \
>                      -cpu cortex-m4 \
>                      -kernel tests/test-armv6m-undef
>                      -d in_asm,cpu,nochain

This is also kind of dubious, because the microbit is
really a Cortex-M0 v6M system. In fact I think it
is just ignoring the -cpu argument and giving you the M0
anyway.

thanks
-- PMM

Re: [Qemu-arm] QEMU user mode for cortex M

[Massimiliano Cialdi]

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On Sat, Mar 16, 2019 at 1:01 PM Alex Bennée <alex.bennee@linaro.org> wrote:
>
>
> Massimiliano Cialdi <cialdi@gmail.com> writes:
>
> > I have my exetutable compiled with
> > /opt/gcc-arm-none-eabi-8-2018-q4-major/bin/arm-none-eabi-gcc -std=gnu11
> > -mcpu=cortex-m7 -mthumb -mfloat-abi=hard -mfpu=fpv5-d16 -fno-common
> > -specs=rdimon.specs -Wl,--cref,-Map=main.map main.c -o main.elf
>
> I thought you wanted to target a cortex-m4?
yes.
I tried to compile it like this.:
/opt/gcc-arm-none-eabi-8-2018-q4-major/bin/arm-none-eabi-gcc
-std=gnu11 -mcpu=cortex-m4 -mthumb  -fno-common -specs=rdimon.specs
-Wl,--cref,-Map=main.map -T prova.ld -O0 -g3 main.c -o main.elf
The linker script is attached

I don't know how to compile with arm-linux-gnueabihf-gcc

>
> Have a look at how test-armv6m-undef is built. It is the simplest
> dumbest M profile image you can build with a kernel that maps to 0 and a
> simple reset vector at the start of the vector table:
I don't want to have to deal with interrupt vectors and memory layouts.
Just see "hallo world!" on the output.



> I don't know what the virt machine defaults to for CPU but I'm fairly
> sure it's not an m-profile CPU.
I had only tried the machine none and virt... I didn't know which one
to choose for cortex M4


> It's hard to say without seeing what your test is doing. However I can force
> a cortex-m4 on a microbit and run the following ok:
>
>   ./qemu-system-arm  -monitor none -display none \
>                      -chardev file,path=test-armv6m-undef.out,id=output \
>                      -semihosting -M microbit \
>                      -cpu cortex-m4 \
>                      -kernel tests/test-armv6m-undef
>                      -d in_asm,cpu,nochain

tried with:
~/Downloads/qemu/qemu-3.1.0/arm-softmmu/qemu-system-arm -d
in_asm,cpu,nochain,unimp,guest_errors -chardev
file,path=prova.out,id=output -machine microbit -cpu cortex-m4
-monitor null -serial null  -semihosting -nographic
-semihosting-config enable=on,target=native  -kernel main.elf
----------------
IN:
0x00000000:  00000000  andeq    r0, r0, r0

R00=00000000 R01=00000000 R02=00000000 R03=00000000
R04=00000000 R05=00000000 R06=00000000 R07=00000000
R08=00000000 R09=00000000 R10=00000000 R11=00000000
R12=00000000 R13=00000000 R14=ffffffff R15=00000000
XPSR=40000000 -Z-- A priv-thread
nrf51_soc.private: unimplemented device write (size 4, value 0x0,
offset 0xfffffe0)
nrf51_soc.private: unimplemented device write (size 4, value 0x0,
offset 0xfffffe4)
nrf51_soc.private: unimplemented device write (size 4, value 0x0,
offset 0xfffffe8)
nrf51_soc.private: unimplemented device write (size 4, value 0x0,
offset 0xfffffec)
nrf51_soc.private: unimplemented device write (size 4, value 0x0,
offset 0xffffff0)
nrf51_soc.private: unimplemented device write (size 4, value
0xffffffff, offset 0xffffff4)
nrf51_soc.private: unimplemented device write (size 4, value 0x0,
offset 0xffffff8)
nrf51_soc.private: unimplemented device write (size 4, value
0x40000000, offset 0xffffffc)
----------------
IN:
0x00000000:  00000000  andeq    r0, r0, r0

R00=00000000 R01=00000000 R02=00000000 R03=00000000
R04=00000000 R05=00000000 R06=00000000 R07=00000000
R08=00000000 R09=00000000 R10=00000000 R11=00000000
R12=00000000 R13=ffffffe0 R14=fffffff9 R15=00000000
XPSR=40000003 -Z-- A handler
qemu: fatal: Lockup: can't escalate 3 to HardFault (current priority -1)

R00=00000000 R01=00000000 R02=00000000 R03=00000000
R04=00000000 R05=00000000 R06=00000000 R07=00000000
R08=00000000 R09=00000000 R10=00000000 R11=00000000
R12=00000000 R13=ffffffe0 R14=fffffff9 R15=00000000
XPSR=40000003 -Z-- A handler
FPSCR: 00000000
Aborted (core dumped)


still no success

best regards
Max


--
Et nunc, auxilium solis, vincam!
Oppugnatio solaris!
VIS!

Massimiliano Cialdi
cialdi@gmail.com

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Re: [Qemu-arm] QEMU user mode for cortex M

[Massimiliano Cialdi]

I did it.

File main.c:

--------8<------------------------
#include <stdio.h>
#include <stdlib.h>

int main(void)
{
    printf("Hallo ARM world!\n");
    exit(0);
}
--------8<------------------------

compiled with:
/opt/gcc-arm-none-eabi-8-2018-q4-major/bin/arm-none-eabi-gcc
-std=gnu11 -mcpu=cortex-m4 -mthumb  -fno-common -specs=rdimon.specs
-Wl,--cref,-Map=main.map  -O0 -g3 main.c -o main.elf

I run it with qemu user mode, and it works:
~/Downloads/qemu/qemu-3.1.0/arm-linux-user/qemu-arm -D prova.out -d
in_asm,cpu,nochain,unimp,guest_errors -cpu cortex-m4 main.elf
Hallo ARM world!


probably works by accident, but I have achieved my goal. Any comment?

best regards
Max


On Sat, Mar 16, 2019 at 9:34 PM Massimiliano Cialdi <cialdi@gmail.com> wrote:
>
> On Sat, Mar 16, 2019 at 1:01 PM Alex Bennée <alex.bennee@linaro.org> wrote:
> >
> >
> > Massimiliano Cialdi <cialdi@gmail.com> writes:
> >
> > > I have my exetutable compiled with
> > > /opt/gcc-arm-none-eabi-8-2018-q4-major/bin/arm-none-eabi-gcc -std=gnu11
> > > -mcpu=cortex-m7 -mthumb -mfloat-abi=hard -mfpu=fpv5-d16 -fno-common
> > > -specs=rdimon.specs -Wl,--cref,-Map=main.map main.c -o main.elf
> >
> > I thought you wanted to target a cortex-m4?
> yes.
> I tried to compile it like this.:
> /opt/gcc-arm-none-eabi-8-2018-q4-major/bin/arm-none-eabi-gcc
> -std=gnu11 -mcpu=cortex-m4 -mthumb  -fno-common -specs=rdimon.specs
> -Wl,--cref,-Map=main.map -T prova.ld -O0 -g3 main.c -o main.elf
> The linker script is attached
>
> I don't know how to compile with arm-linux-gnueabihf-gcc
>
> >
> > Have a look at how test-armv6m-undef is built. It is the simplest
> > dumbest M profile image you can build with a kernel that maps to 0 and a
> > simple reset vector at the start of the vector table:
> I don't want to have to deal with interrupt vectors and memory layouts.
> Just see "hallo world!" on the output.
>
>
>
> > I don't know what the virt machine defaults to for CPU but I'm fairly
> > sure it's not an m-profile CPU.
> I had only tried the machine none and virt... I didn't know which one
> to choose for cortex M4
>
>
> > It's hard to say without seeing what your test is doing. However I can force
> > a cortex-m4 on a microbit and run the following ok:
> >
> >   ./qemu-system-arm  -monitor none -display none \
> >                      -chardev file,path=test-armv6m-undef.out,id=output \
> >                      -semihosting -M microbit \
> >                      -cpu cortex-m4 \
> >                      -kernel tests/test-armv6m-undef
> >                      -d in_asm,cpu,nochain
>
> tried with:
> ~/Downloads/qemu/qemu-3.1.0/arm-softmmu/qemu-system-arm -d
> in_asm,cpu,nochain,unimp,guest_errors -chardev
> file,path=prova.out,id=output -machine microbit -cpu cortex-m4
> -monitor null -serial null  -semihosting -nographic
> -semihosting-config enable=on,target=native  -kernel main.elf
> ----------------
> IN:
> 0x00000000:  00000000  andeq    r0, r0, r0
>
> R00=00000000 R01=00000000 R02=00000000 R03=00000000
> R04=00000000 R05=00000000 R06=00000000 R07=00000000
> R08=00000000 R09=00000000 R10=00000000 R11=00000000
> R12=00000000 R13=00000000 R14=ffffffff R15=00000000
> XPSR=40000000 -Z-- A priv-thread
> nrf51_soc.private: unimplemented device write (size 4, value 0x0,
> offset 0xfffffe0)
> nrf51_soc.private: unimplemented device write (size 4, value 0x0,
> offset 0xfffffe4)
> nrf51_soc.private: unimplemented device write (size 4, value 0x0,
> offset 0xfffffe8)
> nrf51_soc.private: unimplemented device write (size 4, value 0x0,
> offset 0xfffffec)
> nrf51_soc.private: unimplemented device write (size 4, value 0x0,
> offset 0xffffff0)
> nrf51_soc.private: unimplemented device write (size 4, value
> 0xffffffff, offset 0xffffff4)
> nrf51_soc.private: unimplemented device write (size 4, value 0x0,
> offset 0xffffff8)
> nrf51_soc.private: unimplemented device write (size 4, value
> 0x40000000, offset 0xffffffc)
> ----------------
> IN:
> 0x00000000:  00000000  andeq    r0, r0, r0
>
> R00=00000000 R01=00000000 R02=00000000 R03=00000000
> R04=00000000 R05=00000000 R06=00000000 R07=00000000
> R08=00000000 R09=00000000 R10=00000000 R11=00000000
> R12=00000000 R13=ffffffe0 R14=fffffff9 R15=00000000
> XPSR=40000003 -Z-- A handler
> qemu: fatal: Lockup: can't escalate 3 to HardFault (current priority -1)
>
> R00=00000000 R01=00000000 R02=00000000 R03=00000000
> R04=00000000 R05=00000000 R06=00000000 R07=00000000
> R08=00000000 R09=00000000 R10=00000000 R11=00000000
> R12=00000000 R13=ffffffe0 R14=fffffff9 R15=00000000
> XPSR=40000003 -Z-- A handler
> FPSCR: 00000000
> Aborted (core dumped)
>
>
> still no success
>
> best regards
> Max
>
>
> --
> Et nunc, auxilium solis, vincam!
> Oppugnatio solaris!
> VIS!
>
> Massimiliano Cialdi
> cialdi@gmail.com



-- 
Et nunc, auxilium solis, vincam!
Oppugnatio solaris!
VIS!

Massimiliano Cialdi
cialdi@gmail.com