From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([209.51.188.92]:53485) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1h1xhz-0007Ji-60 for qemu-devel@nongnu.org; Thu, 07 Mar 2019 13:25:32 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1h1xhy-00053L-A9 for qemu-devel@nongnu.org; Thu, 07 Mar 2019 13:25:31 -0500 Received: from mail-wr1-x443.google.com ([2a00:1450:4864:20::443]:32920) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1h1xhy-00051u-13 for qemu-devel@nongnu.org; Thu, 07 Mar 2019 13:25:30 -0500 Received: by mail-wr1-x443.google.com with SMTP id i12so18601805wrw.0 for ; Thu, 07 Mar 2019 10:25:29 -0800 (PST) References: <1551978650-23207-1-git-send-email-mateja.marjanovic@rt-rk.com> <1551978650-23207-2-git-send-email-mateja.marjanovic@rt-rk.com> <87imwufv42.fsf@zen.linaroharston> From: Alex =?utf-8?Q?Benn=C3=A9e?= In-reply-to: Date: Thu, 07 Mar 2019 18:25:27 +0000 Message-ID: <87ftryfso8.fsf@zen.linaroharston> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Subject: Re: [Qemu-devel] [PATCH] target/mips: Fix minor bug in FPU List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Aleksandar Markovic Cc: Mateja Marjanovic , "qemu-devel@nongnu.org" , "aurelien@aurel32.net" , Aleksandar Rikalo , "peter.maydell@linaro.org" Aleksandar Markovic writes: >> From: Alex Benn=C3=A9e >> Subject: Re: [PATCH] target/mips: Fix minor bug in FPU >> >> Mateja Marjanovic writes: >> >> > From: Mateja Marjanovic >> > >> > Wrong type of NaN was generated by maddf and msubf insturctions >> > when the arguments were inf, zero, nan or zero, inf, nan >> > respectively. >> > >> > Signed-off-by: Mateja Marjanovic >> > --- >> > fpu/softfloat-specialize.h | 2 +- >> > 1 file changed, 1 insertion(+), 1 deletion(-) >> > >> > diff --git a/fpu/softfloat-specialize.h b/fpu/softfloat-specialize.h >> > index 16c0bcb..647bfbc 100644 >> > --- a/fpu/softfloat-specialize.h >> > +++ b/fpu/softfloat-specialize.h >> > @@ -500,7 +500,7 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatCl= ass b_cls, FloatClass c_cls, >> > */ >> > if (infzero) { >> > float_raise(float_flag_invalid, status); >> > - return 3; >> > + return 2; >> >> Hi, >> >> This changes the behaviour documented above which says: >> >> /* For MIPS, the (inf,zero,qnan) case sets InvalidOp and returns >> * the default NaN >> */ >> >> So if the behaviour is incorrect please update the comment as well. >> Bonus points for a reference to the canonical reference document that >> describes this. >> > > Alex, > > I tested this case (0*inf+nan fused multiply-add/multiply-subtract) on a = MIPS > hardware system, and this patch is right - after the patch QEMU and hardw= are > (MIPS64R6 board) behaviors match. The comment you mentioned probably > just reflects the code, it looks not to be the reference source of inform= ation. > If the patch is accepted, that comments must be changed in the same > patch. I'm perfectly happy to take your word the fix is fine for MIPS - as you say this is part of the rich tapestry of IMPDEF variations on NaN handling ;-) I did have a brief browse through the MIPS Architecture for Programmers (Document Number: MD00083) but couldn't find a decent line about the NaN propagation but if it's somewhere else it would be worth mentioning in the comment. > > This is a MIPS-only-specific change (under "#if defined (TARGET_MIPS)"), = and, > from your point of view, could this be included in MIPS pull request (if = the validity > of the patch is confirmed)? I'd be happy for you to included it (with the matching comment change) in your next PR: Acked-by: Alex Benn=C3=A9e > > Sincerely, > Aleksandar -- Alex Benn=C3=A9e