[U-Boot] [PATCH v3 4/7] MSCC: add support for Luton SoCs

[Gregory CLEMENT <gregory.clement@bootlin.com>]

Hi Daniel,
 
 On lun., déc. 10 2018, Daniel Schwierzeck <daniel.schwierzeck@gmail.com> wrote:
>> +static inline int hal_vcoreiii_train_bytelane(u32 bytelane)
>> +{
>> +	register int res;
>> +
>> +	set_dly(bytelane, 0);	// Start training at DQS=0
>
> no C++ style comments
>
OK
[...]
>> +	for (i = 0; i < 8; i++) {
>> +		DDR[i] = ~i;
>> +		if (DDR[i] != ~i)
>
> __raw_readl(), __raw_writel() ?

OK

[...]
>> +++ b/arch/mips/mach-mscc/include/mach/luton/luton.h
>> @@ -0,0 +1,24 @@
>> +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
>
> this line should begin with a //. Please fix all files in this patch.

As explained in the previous patch /* */ is the correct comment style for
SPDX in C header file

[...]
>> +	/* Wait for lock */
>> +2:	lw	v0, MACRO_CTRL_PLL5G_STATUS_PLL5G_STATUS0
>> +	andi	v1, v0, MACRO_CTRL_PLL5G_STATUS_PLL5G_STATUS0_LOCK_STATUS
>> +	# Keep looping if zero (no lock bit yet)
>
> should be a C style comment

OK

Thanks,

Gregory

-- 
Gregory Clement, Bootlin
Embedded Linux and Kernel engineering
http://bootlin.com